RLDRAM II Controller Core
Features
- Up to 100 percent throughput possible for read or write requests (excluding refresh cycles) using common input/output (CIO) RLDRAM II devices
- Up to 100 percent simultaneous read and write throughput possible (excluding refresh cycles) using separated input/output (SIO) RLDRAM II devices
- Efficient bank management reduces random bank access latency—commands are executed immediately as long as tRC requirements are met
- Pipelined design optimized for high clock rates and minimal routing constraints
- Automatic auto refresh command generation with programmable interval
- Support for burst lengths (BL) of BL2 or BL4
- Support for 288 Mbit and 576 Mbit RLDRAM II devices
- Run-time configurable timing parameters and memory settings
- Support for multiplexed and non-multiplexed address interface to RLDRAM II devices
- Half-rate datapath option available—allows high-rate data throughput with half-rate user interface
- Programmable selection for use of RLDRAM II on-die termination (ODT) and impedance matching resistance
- Supports x9, x18, and x36 devices in any combined data width (18, 36, 72, and so on)
- Available in netlist or source code (Verilog, VHDL)
- Available with multi-port front-end option—provides an eight-port interface to the controller with command reordering and memory test functions
- Optional error correction coding (ECC), read-modify-write, and multi-burst add-on modules are available
- Fast response time and expert technical support provided by Northwest Logic IP designers
Block Diagram
Figure 1 shows the block diagram for the megafunction.
Figure 1. Block Diagram for the Megafunction

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Description
The Northwest Logic RLDRAM II Controller core is designed for use in applications requiring high memory throughput, high clock rates, and full programmability.
The core has been optimized to take advantage of the fast random cycle and fast access times available with RLDRAM II.
The core supports both common and separate data buses and multiplexed and non-multiplexed addressing.
The core accepts commands using a simple local interface and translates them to the command sequences required by RLDRAM II devices. The core also performs all initialization and refresh functions.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings.
The core is available with a half-rate datapath option. This option enables high-rate data throughput with half-rate user interface. The user-side data width is twice as wide as the full rate version of the controller to facilitate high bandwidths at the RLDRAMM II pin interface.
The core is available with an optional multi-port front-end module that provides an eight-port user interface to the controller. This module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port front-end can perform command reordering to achieve maximum SDRAM bandwidth. The multi-port front-end module also includes an extended burst interface and a built-in memory test module.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
Deliverables
- Core (netlist or source code)
- Comprehensive verification suite (source code)
- Complete documentation
- Expert technical support and maintenance updates
Contact Information
For additional information, contact Northwest Logic, Inc. at:
Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
E-mail: ip@nwlogic.com
URL: www.nwlogic.com/
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