PCI Express Compiler: x1, x4, and x8 MegaCore Functions

from Altera

Features

• Feature rich
  • Hard intellectual property (IP) compliant with PCI Express Base Specification 2.0 and 1.1 and with x1, x4, and x8 lane support for endpoint and root port applications
  • Hard IP provides low-power PCI Express solution
  • Optional end-to-end cyclic redundancy code (ECRC) generation/checking and advanced error reporting (AER) for high-reliability applications
• Ease of use
  • Protocol solution available for easy adoption
  • Huge on-chip resource savings and guaranteed timing closure using PCI Express hard IP
  • Easy adoption with no license requirement for hard IP
  • Multiple example designs to jump-start your designs
  • Easy configuration using simple GUI
• Robust solution
  • Industry-compliant IP
  • Support for soft IP on Altera's PCI Express Development Kit, Stratix^® II GX Edition.

General Description

These popular PCI Express MegaCore^® functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. Also, the MegaCore functions are flexible and parameterizable, allowing customization for your specific needs. As an example, the MegaCore functions support a configurable payload, a configurable retry buffer, and optional support for high-reliability features such as ECRC generation/checking and AER.

There are a number of deliverables available to facilitate the easy adoption and integration of the IP core into your design. The PCI Express Compiler includes an endpoint testbench that incorporates a simple root-port bus functional model (BFM) and multiple endpoint example designs. You can use these example designs, available in clear-text source-code (VHDL) and Verilog (HDL), as references to kick-start your design, while the simple root-port BFM is geared to provide an "out of the box" PCI Express experience.

Altera has performed significant hardware testing of the PCI Express x1, x4, and x8 IP MegaCore functions to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCI Express switch chips, and embedded microprocessors. Additionally, the soft IP MegaCore functions were tested at the PCI-SIG compliance workshops and passed with extremely high quality results, including passing 100 percent of the PCI-SIG gold tests.

Figure 1 shows a high-level block diagram of the PCI Express hard IP block.

Figure 1. PCI Express Hard IP Block

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Protocol Solution

The following resources are available to help you easily adopt PCI Express into your design:

• Complete and detailed documentation of the IP core PCI Express Compiler User Guide (PDF)
• Step-by-step instructions to get started with the IP core
• Complete description of the FPGA capabilities
  • Stratix IV GX FPGAs
  • Arria II GX FPGAs
  • Cyclone^® IV GX FPGAs
• Free online training to shorten the learning
  • PCI Express Hard IP Quick Start Guide with SOPC Builder
• Reference designs to jump-start system-level design
  • PCI Express High-Performance Reference Design
  • PCI Express to DDR2 SDRAM Reference Design

Please contact an Altera^® sales representative to get a complete list of platforms tested for compliance checking at PCI-SIG

Device Utilization and Performance

Typical expected performance and utilization figures for this core are provided in the PCI Express Compiler User Guide (PDF).

Technical Support

For technical support on the PCI Express MegaCore functions, please visit the PCI Express MegaCore Support Center. Additional support for MegaCore functions is available in the Altera mySupport online issue tracking system. You may also search for related topics on these functions in the Altera Solutions Database.