x1, x4, x8 PCI Express Cores
Features
- High-performance, easy-to-use core
- Available in x1, x4, x8 lane configurations
- Support for integrated or external discrete PCI Express PHYs
- Flexible data buffer sizing
- Implements all three PCI Express layers (transaction, data link, and physical)
- Support for up to eight virtual channels and eight traffic classes
- Support for independent user and physical interface clock domains
- Complete error-handling support
- Comprehensive status port provides a wealth of diagnostic information that can be used for system-level debug and link stability monitoring
- Push-button timing achieved with minimal routing constraints, even in low-cost, slower speed grade FPGA families
- Provided with comprehensive source code PCI Express verification suite
- PCI Express base specification revision 1.1 compliant
- Fully validated, including PCI-Sig, nSys, NVS, Catalyst SpekChek, and Lecroy CTS certification
- Customization and integration services available
- Available with development boards
- Core source code available
- Available with Windows and Linux drivers
- Available with GUI for Windows
- Fast response and expert technical support provided by experienced Northwest Logic IP designers
Block Diagram
Figure 1 shows the block diagram for the megafunction.
Figure 1. Block Diagram for the Megafunction
Description
The Northwest Logic x1, x4, x8 PCI Express core provides a flexible, high-performance, easy-to-use local interface to the PCI Express bus. The core implements all three layers defined by the PCI Express standard and supports all key PCI Express features, including multiple virtual channels and traffic classes.
The core provides:
- A control interface with consistent timing and function over all modes of operation
- A data interface that connects directly to first-in-first-out (FIFO) interfaces
- Separate clock domain transfers performed by the core for each virtual channel
- Complete error-handling support
- Push-button place-and-route timing with minimal routing constraints
The core is provided with a comprehensive verification suite with complete scripting and random stimulus capabilities that allow you to fully validate your design prior to use in hardware. The core has been extensively verified through ASIC-level testing methodologies and has been integrated in a wide variety of applications.
Also available from Northwest Logic are PCI Express development boards that you can use to quickly prototype a complete PCI Express system. A demo GUI, drivers, and an FPGA reference design are provided with the board.
Northwest Logic also provides customization and integration services to produce complete logic designs or sub-systems.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Supported Altera® Devices |
Speed Grade |
Utilization
Logic Elements |
Performance
(fMAX) |
Parameter Settings |
Stratix® II,
Stratix II GX |
-5 |
6,500
x1 core |
11,000
x4 core |
17,000
x8 core |
Internal (GX) or external PHY
125 MHz |
Contact Northwest Logic |
Stratix,
Stratix GX |
-6 |
6,500
x1 core |
11,000
x4 core |
17,000
x8 core |
Internal (GX) or external PHY
125 MHz |
Contact Northwest Logic |
| Cyclone® II |
-5 |
6,500
x1 core |
1,500 |
- |
External PHY
125 MHz |
Contact Northwest Logic |
| Cyclone |
-6 |
6,500 |
1,500 |
- |
External PHY
125 MHz |
Contact Northwest Logic |
Deliverables
- Core (netlist or source code)
- Comprehensive verification suite (source code)
- Complete documentation
- Expert technical support and maintenance updates
Contact Information
For additional information, contact Northwest Logic, Inc. at:
Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
E-mail: ip@nwlogic.com
URL: www.nwlogic.com/
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