32-Bit PCI Bus Target Interface
Features
- Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
- Supports zero-wait state burst mode data transfer
- Internal write buffer to maximize data bandwidth
- Optional first-in first-out (FIFO) interface
- 33-MHz operating frequency
Block Diagram
Figure 1 shows the block diagram for the 32-bit PCI target interface megafunction.
| Figure 1. Block Diagram |
 |
Description
The 32-bit PCI target interface megafunction provides a user-friendly interface between a target device and a PCI bus. This megafunction is a very compact design that minimizes logic cell count while providing a high-bandwidth data transfer. The megafunction performs all data transfer functions requested by the PCI bus master. To maximize data bandwidth, the megafunction provides an internal write buffer and supports burst mode data transfer. All PCI configuration requests are processed locally by the megafunction.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| EPF10K10 |
-3 |
310 |
0 |
33 MHz |
Non-burst target design |
| EPF6016 |
-2 |
310 |
- |
33 MHz |
Non-burst target design |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Eureka Technology, Inc. at: Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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