64-bit PCI Host Bridge

from Eureka Technology Inc.

Features

• Fully supports PCI specification 2.1 and 2.2 protocols
• Designed for programmable logic devices (PLDs) and ASIC implementations in various system environments
• Supports both 64-bit and 32-bit bus systems
• Fully static design with edge-triggered flip-flops
• Efficient back-end interface for different types of user devices
• Host bridge design includes bus master, bus target, and central system functions
• Generates standard PCI type 0 and type 1 configuration accesses
• Combines bus master and target functions
• Supports zero wait state and user inserted wait state burst data transfer
• Dual write buffer supports write data posting
• User controlled burst and non-burst data transfer
• Automatically handles configuration register read/write access
• Supports user initiated target retry, disconnect, abort, and delayed transactions
• Includes all PCI specific configuration registers

Block Diagram

Figure 1 shows the block diagram for the 64-bit PCI host bridge megafunction.

Figure 1. Block Diagram

The 64-bit PCI host bridge is designed for interfacing the host CPU with the PCI bus. The host bridge consists of three functions: bus master, bus target, and configuration access generation.

A highly efficient and flexible back-end bus interfaces with the system CPU and user defined logic, such as direct memory access (DMA) and memory controllers. The core utilizes the double data buffer design approach that minimizes design gate count and achieves the highest possible data bandwidth at the same time.

The host bridge core allows the central processing unit (CPU) or user logic to initialize the entire system during power-up reset. Configuration Mechanism #1, as defined by the PCI specification, is implemented by the host bridge, and both type zero and type one transactions are supported. This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements. Please contact Eureka Technology or visit Eureka Technology web site for a complete data sheet.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Note:

1. EABs = Embedded array blocks

Contact Information

For additional information, contact Eureka Technology, Inc. at:

Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com