64-Bit PCI Master/Target Interface
Features
- Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
- 64-bit PCI bus
- Zero-wait state burst data transfer
- Includes both bus master and bus target functions
Block Diagram
Figure 1 shows the block diagram for the 64-bit PCI master/target megafunction.
| Figure 1. Block Diagram |
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Description
The 64-bit PCI master/target megafunction interfaces bus mastering devices, such as direct-memory access (DMA) controllers or video coprocessors, to the PCI bus. It processes all data requests from the bus mastering device and translates them into PCI bus requests.
This megafunction is designed for a 64-bit PCI bus system, which doubles the data bandwidth of a 32-bit PCI system. It supports zero-wait state burst transfers and a very long burst length. The megafunction supports up to a 266 Mbytes per second data transfer rate, and both 64-bit and 32-bit data transfers.
The 64-bit PCI master/target megafunction contains the functions of a bus master and a bus target. The device data and status can be accessed as a PCI master or target. All compliant configuration registers are included in the megafunction and all configuration accesses are processed automatically. This megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| EPF10K30A |
-2 |
950 |
0 |
33 MHz |
Contact Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can Eureka Technology, Inc. at: Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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