- Complies with PCI bus specification 2.1 and 2.2
- Converts PCI transactions to industry-standard architecture (ISA) bus transactions
- Functions as a PCI target on a PCI bus
- Functions as an ISA master on an ISA bus
- Maps PCI address space to ISA address space through a base address register
- Supports 16-bit and 8-bit data transfer, memory, and I/O transfers on an ISA bus
- Performs multiple ISA operations to transfer each 32-bit PCI word
- Writes buffer to speed up PCI-to-ISA write transfer
- Supports ISA devices with different speed by using NOWS# and CHRDY signals
- Detects parity generation and parity error on PCI bus
- Includes all PCI-specific configuration registers
- Fully synchronous design. No gated clock or transparent latch. All flip-flops are rising-edge triggers
Figure 1 shows the block diagram for the PCI-to-ISA bridge megafunction.
|Figure 1. Block Diagram|
The PCI-to-ISA bridge functions as a PCI target on the PCI bus. PCI transactions addressed to this target are forwarded to the ISA bus. If it is a read transfer, the core waits for all read data from the ISA slave and returns the data to the PCI bus. If it is a write transfer, the core posts the write data to its internal write buffer, terminates the PCI bus, and then writes the data to the ISA slave.
With a typical PCI bus running at 33 MHz, this core operates the ISA bus at one-fourth the frequency of the PCI bus. The ISA bus operates at 8.33 MHz.
The PCI-to-ISA bridge core supports 8-bit and 16-bit ISA bus devices, while the PCI bus is 32-bits wide. The core is capable of taking one PCI transfer and converting it into four or two transfers on the ISA bus.
This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
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