from Northwest Logic, Inc.
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Features
- High-performance, easy-to-use PCI core
- Achieves push-button timing with minimal routing constraints
- Minimal size
- Supports 33/66 MHz, 32/64-bit operation
- Available in master/target and target-only configurations
- Available in host and peripheral versions
- User-expandable configuration space can be loaded from EEPROM
- Includes Northwest Logic's PCI-X/PCI Verification Suite (in source)
- Optimal scatter-gather DMA module available
- Source code available
- Customization and integration services available
- PCI Local Bus Specification Revision 3.0 compliant
- Fast response, expert technical support provided by Northwest Logic IP designers
Block Diagram
Figure 1 shows a block diagram of the megafunction.
Figure 1. PCI Core Block Diagram
Description
Northwest Logic's PCI core is specifically designed for ease of use:
- Shields the user from the complexities and timing issues of the PCI bus
- Control interface has consistent timing and function over all modes of operation
- Data interface connects directly to first-in first-out (FIFO) interfaces
- Provides complete error-handling support
- Achieves push-button timing with minimal routing constraints
The PCI core implements the front-end functions of a PCI design, giving you complete control of back-end functionality. This flexibility is further enhanced with a user-expandable configuration space. The PCI core supports automatic loading of the configuration space using an EEPROM.
Northwest Logic also offers a drop-in scatter-gather DMA module to enable more complex DMA-based systems to be quickly developed.
The PCI core is available in several versions including 32- or 64-bit, target-only or master/target, and peripheral or host
The core is provided with Northwest Logic's PCI-X/PCI comprehensive Verification Suite with complete scripting and random stimulus capabilities enabling the user design to be fully validated prior to use in hardware.
Northwest Logic also provides customization and integration services to produce complete logic designs.
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | ||||||
| Supported Altera® Devices | Speed Grade |
Utilization |
Performance (fMAX) |
Parameter Settings | ||
|---|---|---|---|---|---|---|
| Stratix® II, Stratix II GX |
-5 | 600 32-bit target only |
750 64-bit target only |
1,200 64-bit master/target |
66 MHz | Contact Northwest Logic |
| Stratix, Stratix GX |
-6 | 600 32-bit target only |
750 64-bit target only |
1,200 64-bit master/target |
66 MHz | Contact Northwest Logic |
| Cyclone® II | -7 | 600 32-bit target only |
750 64-bit target only |
1,200 64-bit master/target |
66 MHz | Contact Northwest Logic |
| Cyclone | -7 | 600 32-bit target only |
750 64-bit target only |
1,200 64-bit master/target |
66 MHz | Contact Northwest Logic |
Deliverables
- Core (netlist or source code)
- Northwest Logic's comprehensive Verification Suite (source code)
- Complete documentation
- Expert technical support and maintenance updates
Contact Information
For additional information, contact Northwest Logic at:
Northwest Logic, Inc.
1100 NW Compton Drive, Ste. 100
Beaverton, OR 97006
Tel: (503) 533-5800, x309
Fax: (503) 533-5900
E-mail: ip@nwlogic.com
URL: www.nwlogic.com
