Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
   Interfaces & Peripherals
          Peripherals
          PCI
          PCI Express
          Memory Controllers
          USB
          PCMCIA
          Ethernet
          I2C
          CAN
          PowerPC Bus
          HyperTransport
          RapidIO
          SerialLite
          Additional Functions
          Consortiums
          Literature
   DSP
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

PCI Express

from PLDA

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • PCI Express Specification 1.0a compliant
  • 4x lane PCI Express core
  • Suitable for root complex, bridge, switch, and endpoint designs
  • 64-bit, 125-MHz interface
  • Upstream and/or downstream mode for link initialization
  • Up to eight virtual channels (VC)
  • Configurable receive (RX), transmit (TX), and retry buffer size
  • Intel PIPE (16-bit mode) compliant
  • Optional backend interface on user’s clock domain
  • Supports up to 4 KB data payload size
  • Supports all message, completion, memory, and I/O requests
  • Highly optimized RX/TX back-end interface for maximum effective throughput
  • Implements type 0 configuration space for endpoint designs
  • Implements type 1 configuration space for root, switch, and bridge designs
  • Up to 6 BARs plus expansion ROM available for endpoint
  • All I/O and memory windows implemented for root, switch, and bridge
  • All power management states and associated logic implemented
  • Supports legacy PCI Power Management

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. PCI Express Core Function



View full detail (55KB)

Description

The PCI Express soft IP core from PLDA is a highly parameterizable module that implements all three digital layers of the PCI Express specification. The core is designed for an utilization in endpoint, bridge, root port, and switch designs. The core benefits from an ASIC verification methodology and is provided with a complete set of tools to allow easy integration in user designs.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
LEs Memory
EP1SGX40 -5 13,500 16.5 KB RAM 125 MHz 4x lane endpoint, 2 VC, 2 BAR, 512 byte payload
EP1SGX25 -5 11,000 8 KB RAM 125 MHz 1x lane endpoint, 2 VC, 2 BAR, 1 KB payload

Deliverables

Core synthesis files (encrypted VHDL or Verilog for Quartus® II software)
Pre-compiled simulation libraries for ModelSim® IP Wizard:

  • Customization assistant
  • Constraint file generator

Verification Environment

  • Testbench pre-compiled simulation libraries for ModelSim software 
  • VHDL/Verilog test scripts and compliance checklist

Software Resources

  • Evaluation PCI device driver
  • API source code
  • GUI applications with source code
  • Reference designs that are ready for hardware implementation
  • Documentation, including a user's guide and design guide
  • One-year technical support and maintenance with free upgrades

Contact Information

For additional information, contact:

PLDA
Parc Club du Golf
Bat 11, rue Guillibert
13856 Aix-en-Provence Cedex 3, France
Telephone (USA): 1-866-513-0362 (toll free)
Telephone (International): +33-(0)-442-393-600
Fax (International): +33-(0)-442-394-902
Email: email@plda.com
URL: http://www.plda.com

  Please Give Us Feedback