PCI-X Master/Target Core 32/64-Bit
Features
- Standards compliance
- PCI-X addendum to PCI local bus specification (revision 1.0b)
- PCI power management (revision 1.1)
- General features
- 32- or 64-bit PCI-X master/target interface
- Supports bus speeds up to 133 MHz
- Multi-function core can implement up to four independent functions
- Full-support 64-bit addressing
- Built-in support for in-site programming through JTAG interface
- Configuration
- Supports all required and optional type 0 configuration registers
- Configuration space can be mapped in a base address
- Up to six base address registers (BARs) plus expansion ROM
- Up to 32 user-defined configuration registers
- Data transfer
- Supports burst memory and I/O transfers with zero wait-state insertion
- Supports all memory and I/O commands
- Supports interrupt acknowledge cycles in target mode
- Can insert wait-states and generate all types of terminations
- Direct memory access (DMA)
- Up to four independent DMA channels with rotating priority
- Flexible back-end interface can directly connect first-in first-out (FIFO) devices
- Can generate all existing PCI-X commands
- Optional scatter-gather support
- 64-bit data transactions are dynamically negotiated
- Split transactions are fully supported on all DMA channels
- Device families targeted
- Stratix® devices; -5 and -6 speed grades
- APEX™ II devices
- Device resource utilization
- 3,500 logic elements (LEs) (typical)
- 100 I/O pins
- Memory usage: none
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. PCI-X Core Function
Description
PLDApplications' PCI-X core provides programmable logic device (PLD) and ASIC designers with a versatile and integrated solution to interface any user application or system to 32- or 64-bit PCI-X peripheral devices. Moreover, the PCI-X core is fully programmable and customizable, easily adaptable to run in any PCI-X environment, and provides features that can be enabled or disabled to suit specific needs.
As shown in Figure 1, PLDApplications' PCI-X core is built around target and master state machines that control all operations to ensure coherence and synchronization with PCI-X bus operation. Data transfer is operated by a 32- or 64-bit bidirectional registered datapath.
Although the PCI-X core primarily targets the add-on card market (including PLDApplications' own development and prototyping boards), it can be beneficial in virtually all types of applications, including data acquisition, imaging, industrial controls, and communication system designs.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
(fmax) |
| LEs |
I/O Pins |
| EP1S25 |
-5 |
3,500 (typical) |
100 |
133 MHz |
| EP1S25 |
-6 |
3,500 (typical) |
100 |
100 MHz |
| EP2A25 |
-7 |
3,500 (typical) |
100 |
66 MHz |
Deliverables
- PCI-X core synthesis library
- Encrypted VHDL or source code PCI wizard
- Customization assistant and constraints file generator
- PCI-X core behavioral models
- Simulation libraries for ModelSim® software and ActiveHDL
- PCI-X script-based VHDL testbench—complete simulation environment
- Reference design
- Documentation
- Getting started guide, core user's guide, and testbench user's guide
- Software development kit for Windows 95, 98, NT, and 2000
- PCI device driver, application program interface (API) source code, GUI source code, and PCI exerciser software
- One year of technical support and maintenance
- Includes core upgrades, reference designs, and service hotline
Contact Information
For additional information, contact:
PLDA
Parc Club du Golf
Bat 11, rue Guillibert
13856 Aix-en-Provence Cedex 3, France
Tel. (USA): 1-866-513-0362 (toll free)
Tel. (International): +33-(0)-442-393-600
Fax (International): +33-(0)-442-394-902
E-mail: email@plda.com
URL: http://www.plda.com
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