CZ80SIO Serial I/O Controller
Features
- Two independent, full duplex channels with separate control and status lines for modems or other devices
- Data rate in the x1 clock mode of 0.0 to 2.0 Mbps with a 10-MHz clock
- Asynchronous protocols; everything necessary for complete messages in 5, 6, 7, or 8 bits/characters, includes variable stop bits and several clock-rate multipliers; break generation and detection; parity overrun; and framing error detection
- Synchronous protocols; everything necessary for complete bit- or byte-oriented message in 5, 6, 7, or 8 bits/characters; automatic cyclic redundancy code (CRC) generation/checking; sync character and zero insertion/detection; abort generation/detection; and flag insertion
- Quadrupled buffered receiver data registers, doubled buffered transmitter registers
- Highly sophisticated and flexible daisy-chain interrupt vectoring for interrupt without external logic
Block Diagram
Figure 1 shows the block diagram for the CZ80SIO controller megafunction.
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Description
The CZ80SIO Serial I/O Controller megafunction implements a dual-channel data communication interface with extraordinary versatility and capability. Its basic functions are a serial-to-parallel/parallel-to-serial converter/controller that can be programmed by a CPU for a broad range of serial communication applications.
Designed to run at frequencies of up to 115 MHz on a typical 0.35-micron process, the CZ80SIO uses less than 13,000 gates depending on the technology. At a typical 0.5-micron process, it runs at frequencies of up to 120 MHz and it uses less than 11,000 gates. The CZ80SIO controller is a technology-independent design that can be implemented in a variety of process technologies.
The CZ80SIO controller is a testable, microcode-free design developed for reuse in ASICs and FPGAs. A complete verification environment helps you verify the functioning and compliance of the megafunction, and additional aids for system-on-chip simulation are available.
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Elements (1) |
EABs (2) |
| Cyclone® (EP1C6) |
-6 |
3,271 |
- |
124 MHz |
Contact CAST |
| Stratix® (EP1S10) |
-5 |
3,271 |
- |
129 MHz |
Contact CAST |
| Stratix II (EP2S15) |
-3 |
2.666 |
- |
267 MHz |
Contact CAST |
| ACEX® 1K (EP1K100) |
-1 |
3,830 |
- |
77 MHz |
Contact CAST |
Notes:
- The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
- EABs = Embedded array blocks
Deliverables
- Post-synthesis EDIF netlist
- Assignment and configuration
- Symbol file
- Include file
- Testbench
- Vectors for testing the functionality of the megafunction including expected results
- Documentation
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: OpenCore@cast-inc.com
URL: www.cast-inc.com
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