H16750S
Features
- Capable of running all existing 16450 and 16550 software
- Fully synchronous design, with all inputs and outputs based on the rising edge of the clock
- In first-in first-out (FIFO) mode, the transmitter and receiver are each buffered with up to 256-byte FIFO buffers to reduce the number of interrupts presented to the CPU
- Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
- Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
- Independently controlled transmit, receive, line status, and data set interrupts
- Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16x clock
- Independent receiver clock input
- Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
- Programmable Auto-CTSn and Auto-RTSn
- In Auto-CTSn mode, CTSn controls the transmitter
- In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
- Serial Port has an optional Infrared Data Association (IrDA) data port
- Fully-programmable serial interface characteristics, including:
- 5-, 6-, 7-, or 8-bit characters
- Even-, odd-, or no-parity bit generation and detection
- 1-, 1½-, or 2-stop bit generation
- Baud generation
- False start bit detection
- Complete status register
- Internal diagnostic capabilities, including loop-back controls for communications link fault isolation
- Fully prioritized interrupt system controls
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. Block Diagram
 Click for full detail (239KB)
Description
The H16750 is a standard synchronous universal asynchronous receiver transmitter (UART) providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16750 can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.
Developed for easy reuse in ASIC and FPGA applications, the H16750 is available optimized for several technologies with competitive utilization and performance characteristics.
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Target Device |
Speed Grade |
Utilization |
Performance
f(MAX) |
| LCs |
EABs |
I/O Pins |
| EP20K30E |
-1 |
734 |
2 |
39 |
65 MHz |
| EP1K30 |
-1 |
732 |
2 |
39 |
61 MHz |
| EP1S10 |
-7 |
645 |
2 |
39 |
105 MHz |
Deliverables
- EDIF netlist
- Assignment & configuration file
- Symbol file
- Include file
- Vectors for testing the functionality of the megafunction including expected results
- Documentation
Contact Information
For additional information, contact CAST, Inc.:
11 Stonewall Court
Woodcliff Lake, NJ 07677
Tel: 201-391-8300
Fax: 201-391-8694
E-mail: info@cast-inc.com
WWW: www.cast-inc.com
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