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MD5

from CAST, Inc.

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • RFC 1321 compliant
  • Suitable for data authentication applications
  • Fully synchronous design
  • Also available in VHDL or Verilog source code 

Block Diagram

Figure 1 shows the block diagram for the MD5 megafunction.

Figure 1 shows the block diagram for the MD5 megafunction

Description

This megafunction is a fully compliant hardware implementation of the MD5 Message-Digest Algorithm, suitable for a variety of applications. It computes a 120-bit message digest for messages of up to (264 – 1) bits.

The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 by 32-bit word) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
Logic Elements (1) Memory
FLEX® 10K50 -1 2,262 2 EABs 25 MHz Contact CAST
ACEX® 1K50 -1 2,261 2 EABs 26MHz Contact CAST
APEX™ 20K60E -1 2,285 2 ESBs 39 MHz Contact CAST
APEX II 2A15 -7 2,290 2 ESBs 60 MHz Contact CAST
Cyclone™ 1C20 -6 1,527 1 M4K 69 MHz Contact CAST
Stratix® 1S20 -5 1,527 1 M4K 69 MHz Contact CAST
Stratix II 2S60 -3 1,259 1 M4K 115 MHz Contact CAST

Note to Table 1:

  1. The Logic Element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: info@cast-inc.com
URL: http://www.cast-inc.com

  

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