nflashctrl NAND Flash Memory Controller

from CAST, Inc.

Features

• Supports up to eight memory units:
  • Up to eight chip-select and write-protection signals
  • Different memory for each channel
• Adapts to a variety of system and memory types:
  • Three/Four address cycles
  • Eight/Sixteen IO memory support
  • Error correction code (ECC) calculation turn on/off
  • Address mode
  • Ready/Busy edge detection
  • Protected area
  • Interrupt request turn on/off
  • Read/Write pulse time
• Offers configurable timing details
• Has power-save mode for low-power applications
• Provides area erase/write protection
• Utilizes 256 bytes of block ECC calculation
• Gives OK and ERROR responses
• Employs an AMBA™ advanced high-performance bus (AHB) slave interface
  • 32-bit or 16-bit data bus
  • Burst transaction support

Block Diagram

Figure 1 shows the block diagram for the nflashctrl NAND Flash Memory Controller

Description

The NFlashCtrl megafunction implements a flexible controller for NAND flash memory.

The full-featured megafunction manages the read/write interactions between a master host system and up to eight NAND Flash memory units. It uses the standard AMBA AHB for easy integration with these systems (other standard interfaces are also available).

Configurable features and internal configuration registers make it easy to model timing and adapt the megafunction for efficient operation with a variety memory device types. An internal ECC calculator helps detect errors, and a power-save mode makes the NFlashCtrl megafunction suitable for low-power applications.

The megafunction has been rigorously verified and provides competitive speed and area results, for example, with a 0.18µ ASIC process it uses just 5,817 gates and runs at 333 MHz.

The NFlashCtrl megafunction is developed for reuse in ASICs and FPGAs. It is fully synchronous with positive-edge clocking, has no internal three-state buses, and uses a synchronous re-set, so scan insertion is straightforward. The included verification package features bus models for the AHB master and NAND flash devices to help designers verify the functioning and compliance of the megafunction.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Notes to Table 1:

1. The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus^® II software.
2. EABs = Embedded array blocks

Deliverables

• Post-synthesis EDIF netlist
• Assignment and configuration
• Symbol file
• Include file
• Testbench
• Vectors for testing the functionality of the megafunction including expected results
• Documentation

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 201-8694
Email: info@cast-inc.com
URL: http://www.cast-inc.com