D16550 - Universal Asynchronous Receiver/Transmitter with 16 Bytes FIFO

from Digital Core Design

 

Features

• Software compatible with 16450 and 16550 UARTs
• Two modes of operation: UART mode and first in first out (FIFO) mode
• In the FIFO mode, transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
• Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
• In UART mode, receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Independently controlled transmit, receive, line status, and data set interrupts
• False start bit detection
• 16-bit programmable baud generator
• Independent receiver clock input
• Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1½-, or 2-stop bit generation
  • Baud generation
• Complete status reporting capabilities
• Line-break generation and detection. Internal diagnostic capabilities
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Core can be fully customized to better meet customer requirements

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1. D16550 — Universal Asynchronous Receiver/Transmitter with 16 Bytes FIFO

Click for full detail (71 KB)

Description

The D16550 is a UART soft core that is functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or a Modem, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, over-run, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16× clock for driving the internal transmitter logic. Provisions are also included to use this 16× clock to drive the receiver logic. The D16550 has complete Modem control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization
Device	Speed Grade	Utilization		Performance (fMAX)	Parameter Setting
		LEs	EABs
Stratix™	-5	475	2	196 MHz	Contact DCD
APEX™ 20KE	-1	504	2	100 MHz	Contact DCD
APEX 20KC	-7	504	2	135 MHz	Contact DCD
APEX II	-7	552	2	133 MHz	Contact DCD

Deliverables

Hardware description language (HDL) source code package includes:

• VHDL or Verilog source code:
• VHDL or Verilog test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim^® automatic simulation macros
  • Full tests with reference responses
• Synthesis scripts

Encrypted Megafunction package includes:

• EDIF or Text Design File (.tdf) netlist optimized for particular technology
• Core instantiation inside Quartus^® II or MAX+PLUS^® II software environments
• Symbol, include, assigments, and configuration files
• Compilation, simulation, and programming ready project

Each package includes:

• Technical documentation
  • Installation notes
  • HDL core specification
  • Data sheet
• Example application
• Technical support
  • Intellectual property (IP) core implementation support
  • Three months of maintenance, including phone and e-mail support

Contact Information

For additional information, contact Digital Core Design at:

Wroclawska 94
41-902 Bytom
Poland
Tel: +48 32 2828266
Fax: +48 32 2827437
E-mail: info@dcd.pl
http://www.digitalcoredesign.com