AHB Master
Features
- Supports the advanced high-performance bus (AHB) bus interface to the ARM® CPU
- User interface designed for high-speed access to any slave devices on the AHB
- User-specified single or burst data access on the AHB interface and user interface
- Handles wait-state insertion by any slave devices
- Automatic bus arbitration
- Supports all slave device responses:
OKAY, RETRY, SPLIT, and ERROR
- No delay insertion on data transfer between user interface and AHB
- Supports bus parking
- Efficient user interface optimized for on-chip data communication
- User interface matches seamlessly with Eureka Technology direct memory access (DMA) controller or PCI bridge megafunctions
- Optimized for ASIC and programmable logic device (PLD) implementations, including Altera® ExcaliburTM PLDs
Block Diagram
Figure 1 shows a block diagram for the megafunction.
| Figure 1. Block Diagram |
 |
Description
The AHB master megafunction is an interface unit that allows user logic to initiate a data transfer on the AHB. The user specifies the type of transaction to be executed on the AHB through a user-friendly interface. The bus master is optimized to interface with DMA and PCI bus bridge functions to initiate data transfer on the AHB.
Once the user request is received, the bus master automatically arbitrates for the AHB and executes the transaction on the AHB using the AHB protocol. Data received from the AHB is returned to the user interface with no delay.
The bus master handles all four types of slave responses and slave wait states. In the event of RETRY and SPLIT, the bus master automatically re-issues the transaction until all data is transferred.
This megafunction is available in AHDL, Verilog, and VHDL, as well as netlist format. Megafunction sizes vary with features and customization. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Modifiable Parameters
Eureka Technology can customize the design according to specific user requirements. Contact Eureka Technology or visit their web site for more information.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX®
APEXTM
ACEXTM |
|
200 |
0 |
75 MHz |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
USA
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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