DMA Controller for AHB
Features
- Multiple independent DMA channels with direct advanced high-performance bus (AHB) interface
- DMA transfers between AHB memory devices and I/O ports
- Scatter-gather allows DMA to merge multiple data source to contiguous space
- Supports both hardware initiated transfer and software initiated transfer
- Supports burst transfer to maximize data bandwidth
- Automatic address increment or decrement
- Interrupt generation on transfer completion
- Bus interface designed for high-speed access to any slave devices on the AHB
- Handles wait state insertion by any slave devices
- Supports all slave device responses: OKAY, RETRY, SPLIT, and ERROR
- Supports bus parking
- Efficient user interface optimized for on-chip data communication
- User interface matches seamlessly with Eureka Technology DMA controller or PCI bridge
- Optimized for ASIC and programmable logic device (PLD) implementations, including Excalibur™ PLD
Block Diagram
Description
The DMA controller is designed to operate directly on the AHB. It contains multiple channels that can be programmed independently. Two types of DMA transfers are supported by the DMA controller. Type 0 DMA is designed for transferring data between two locations that reside on the AHB. Type 1 DMA is designed for transferring data between AHB and a dedicated I/O bus. Each channel has dedicated interface to its I/O device and all channels shares the same interface to the AHB.
To initiate a DMA transfer, the user programs the source address, destination address, transfer count, and other control information to the DMA channel through a dedicated port. Once it is programmed, DMA can be started either by a hardwire input signal or under software control.
Type 0 DMA transfer is designed for transferring data between memory locations that reside on the AHB bus. Once the transfer is started, the DMA controller arbitrates for AHB ownership. Once it receives bus ownership, it reads the source data from the AHB, using burst transfer when possible to maximize memory bandwidth. Data is stored temporarily in a local buffer. The DMA controller then re-arbitrates for bus ownership to write data from the local buffer to the destination address on AHB. The source address and destination address are then incremented and the transfer count decremented by the number of data words transferred. The process is repeated until the transfer count reaches zero.
Type 1 DMA transfer is designed for transferring data between the AHB and the channel's dedicated I/O port. In type 1 transfers, data passes through the DMA controller without using the local data buffer. Each DMA channel has a dedicated I/O port for data transfer. To transfer data from the AHB to the I/O port, the controller initiates a read access on the AHB based on the source address. Data received from the AHB is then driven on the I/O port immediately. To transfer data from the I/O port to the AHB, data is inputted to the I/O port when DMA starts. The DMA controller initiates a write access on the AHB destination address. Data on the I/O port is then driven on the AHB to write to the destination.
The DMA controller can be programmed to use single, burst of 4, or burst of 8 words to transfer data. If the transfer count programmed by the user is more than one burst size, the DMA controller issues multiple requests to transfer all the data. The DMA controller relinquishes the AHB and re-arbitrates for the bus again between each burst transfer so that other devices on the bus receive their fair share of memory bandwidth on the AHB.
The DMA controller implements scatter gather DMA chaining. A pointer to a DMA link list can be programmed in the control register. At the end of the DMA transfer when transfer count reaches zero, the controller automatically loads a new set of DMA transfer by reading from the AHB address pointed to by the link list pointer. User can set up many different DMA transfer by providing a link list in memory and have the controller execute each DMA transfer sequentially. Scatter gather is useful for merging data from different data locations into one contiguous location.
This megafunction is available in AHDL, Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements. Please contact Eureka Technology or visit Eureka Technology web site for a complete data sheet.
Modifiable Parameters
Eureka Technology can customize the design according to specific user requirements. Contact Eureka Technology or visit their web site for more information.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for
the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
Embedded Array Blocks (EABs) |
| FLEX®,
APEX™, ACEX® |
3000 |
- |
0 |
75 MHz |
Contact Eureka Technology |
Contact Information
For additional information, you can contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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