- Functionally compatible with 16550
- Supports character (16450) and first-in first-out (FIFO) (16550) mode operations
- Designed and optimized for programmable logic device (PLD) and ASIC implementation
- Synchronous design with edge-triggered flip-flops based on system clock input
- 16-byte FIFO for transmitter and receiver reduces the number of interrupt to the central processing unit (CPU)
- Independently controls transmit, receive, line status, and data set interrupts
- Synchronous input sampling timed by internal receiver clock
- Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
- False start bit detection
- Complete status reporting capabilities
- Generates and detects line breaks
- Internal loopback
Figure 1 shows the block diagram for the UART megafunction.
|Figure 1. Block Diagram|
The UART performs serial-to-parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the CPU. The EP600 device supports both character mode (16450) and FIFO mode (16550) operations. Default operation is in the character mode so that when it powers up, the universal asynchronous receiver/transmitter (UART) is compatible with the 16450. When the FIFO mode is activated, it allows 16 bytes of data to be stored to receive or transmit data.
This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Device Utilization Example
Table 1 shows the typical device utilization results for the megafunction.
|Table 1. Typical Device Utilization for the Megafunction|
|Logic Cells||EABs (1)|
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