PowerPC to PCI Host Bridge
Features
- Compliant with PCI Local Bus Specification, Revision 2.2
- Designed for programmable logic device (PLD) and application-specific integrated circuit (ASIC) implementations in various system environments
- Interface directly with a PowerPC microprocessor
- Combined host bridge, bus master, and bus target functions in one megafunction
- 32-bit bus master and target support
- Supports burst transfer to maximize memory bandwidth
- Zero-wait state peripheral component interconnect (PCI) data transfer
- Supports target retry, disconnect, and target abort
- Automatic transfer restart on target retry and disconnect
- Concurrent bus master and target function
- Generate standard peripheral component interconnect (PCI) type 0 and type 1 configuration access
- High-speed bus request and arbitration
- Supports all PCI-specific configuration registers
Block Diagram
Figure 1 shows the block diagram for the PowerPC to PCI Host Bridge megafunction.
| Figure 1. Block Diagram |
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Description
The PowerPC to PCI Host Bridge is a bus interface unit designed for efficient interface between the PowerPC microprocessor and the PCI bus. It contains the functions of a bus master, bus target, and the ability to initiate configuration access all in one megafunction. It performs all the data transfer functions necessary for the PowerPC central processing unit (CPU) to access data on the PCI bus. It supports burst data transfer to maximize data bandwidth. The target function allows other PCI masters to access system resources on the CPU local bus. It supports high-speed bus request and arbitration to minimize transfer latency.
Single and burst data transfer are supported both as bus master and bus target. All data transfers on the PCI bus can be accessed through the CPU local bus. Many design options are possible on the host bridge.
This megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| FLEX 10K |
- |
1,000 |
0 |
33 MHz |
Contact Eureka Technology |
| FLEX 6000 |
- |
1,000 |
0 |
33 MHz |
Contact Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Eureka Technology, Inc. at: Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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