System Controller
Features
- Designed for programmable logic device (PLD) and ASIC implementation
- Fully static design with edge-triggered flip-flops
- Different version supports ARM-based embedded processor PLDs, i960, PowerPC, and SH2-SH4 microprocessors
- Fully integrated single-chip design provides complete system level functions for all external data access
- Replaces multiple discrete devices on the system
- Flexible design adapts to different system requirements
- Two different clock domains for the central processing unit (CPU) and PCI bus interfaces
- Supports concurrent data transfer between the CPU, system memory, direct memory access (DMA), and PCI bus
- Distributes system control register in each functional block
- On-chip connection to user-defined logic blocks
Block Diagram
Figure 1 shows the block diagram for the system controller megafunction.
| Figure 1. Block Diagram |
 |
Description
The system controller core connects the system CPU to system memory, PCI bus, I/O ports, and external communication links. While the CPU's task in the system is to process data, the system controller's main function is to coordinate data movement in the system. The system controller contains all the major functional modules required for most system-on-a-chip (SOC) applications. The entire system control function can be easily integrated into a single ASIC or PLD.
The system controller contains the following: SDRAM controller, PCI bridge, direct memory access (DMA) function, universal asynchronous receiver/transmitter (UART), bus arbiter and system control registers. These modules, which are internal to the system controller, are directly connected to each other to achieve high-performance and concurrent data movement between various source and data destinations. Since each module is implemented as synthesizable hardware description language (HDL) code, each function can be reconfigured or modified as required. All modules are designed with a common interface, and the connectivity between them can be easily modified to meet different system requirements. Modules that are unneeded for specific applications can be removed from the core to minimize die size and gate count. Different system controllers are available for different CPU types. Currently, the CPUs supported include: I960, PowerPC 603, 604, 740, 750, MPC8260, 860, Hitachi SH2, SH3, and SH4. More CPU interfaces will be added in the near future as required. The CPU bus can be 32-or 64-bits wide. Burst data transfer is supported by the system controller.
This megafunction is available in Altera description hardware language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize designs according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Device Utilization Example
Table 1 shows the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX
APEX
ACEX |
|
Varies
6000 and above |
0 |
Varies |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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