from Altera Corporation
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The Serial RapidIO® (SRIO) standard was adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. SRIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical medium attachment (PMA)—such as XAUI for the 3.125-Gbps data rate.
Features
- Feature rich
- Physical, transport, and logical layer separations (modular architecture)
- 1.25-, 2.5-, 3.125-, and 5.0-Gbps lane rates -x1, x4 link widths
- Physical layer based on embedded transceivers or with parallel XGMII interface to external transceivers
- Easy to use
- MegaWizardTM Plug-In Manager GUI allows easy manual optimization of parameters such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis
- Easy configuration provides ways to reduce resource utilization to create smaller MegaCore® function variations depending on application needs
- SOPC Builder support
- Robust solution
- End-point intellectual property (IP) core, testbenches with proven interoperability with leading digital signal processor and switch vendors
- RIOLAB certified RapidIO IP
- Compliant to RapidIO specification, Revision 1.3 and 2.1
For a system-level integration-ready solution, you can save several man-months of design time by selecting all RapidIO layers—including features such as address translation and simple Avalon®-Memory-Mapped (MM) and Avalon-Streaming (ST) FIFO interfaces.
Protocol Solution
Figure 1 shows an example of a system built using SOPC Builder with a Nios® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various end points and also configure the capability address registers of the endpoints and the MegaCore® function.
Figure 1. A Complete SRIO System
- Detailed documentation on how to use the IP core
- Complete description of Altera® device capabilities
- Reference designs for quick and easy design start
- OpenCore Plus evaluation
- Use the Altera OpenCore Plus evaluation flow to test drive this IP core.
Technical Support
For technical support on the RapidIO MegaCore function, please visit the RapidIO MegaCore Support Center. Additional support for the MegaCore function is available in the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
A web-based technical training on configuring the SRIO MegaCore function is also available.
