RapidIO MegaCore Function

from Altera

The RapidIO^® standard was adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA) such as XAUI or CEI for up to 6.25 Gbaud data rate.

Altera Offers Two Distinct RapidIO MegaCore Functions

• RapidIO II MegaCore^® Function complies with the RapidIO Specification Revision 2.2
  • Physical, transport, and logical layer separations (modular architecture)
  • IDLE2 sequence - long control symbol
  • 1.25, 2.5, 3.125, 5.0 and 6.25 Gbaud lane rates with 1x, 2x, and 4x link widths
• RapidIO MegaCore Function complies with the RapidIO Specification Revisions 1.3 / 2.1
  • Physical, transport, and logical layer separations (modular architecture)
  • IDLE1 sequence - short control symbol
  • 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1x and 4x link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO MegaCore function user guides.

Features

• PHY based on embedded transceivers
• Easy to use
  • MegaWizard^TM Plug-In Manager GUI allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis
  • Easy configuration provides ways to reduce resource utilization to create smaller MegaCore function variations depending on application needs
  • Qsys Altera's System Integration Tool for system interconnect
• Robust solution
  • End-point intellectual property (IP) core, testbenches with proven interoperability with leading digital signal processor and switch vendors
  • Compliant to RapidIO specification, Revision 1.3 / 2.1 and 2.2
  • RIOLAB certified RapidIO Revision 1.3 MegaCore function

For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features such as address translation and simple Avalon^® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) FIFO interfaces.

Protocol Solution

Figure 1 shows an example of a system built using Qsys Builder with a Nios^® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various end points and also configure the capability address registers of the endpoints and the MegaCore function.

Figure 1. A Complete SRIO System

• Detailed documentation on how to use the IP core
  • RapidIO II MegaCore Function User Guide (PDF) 
  • RapidIO MegaCore Function User Guide (PDF)
  • MegaCore IP Library Release Notes and Errata (PDF)
• Complete description of Altera^® device capabilities
  • Stratix^® V FPGAs
  • Stratix IV FPGAs
  • Stratix II GX FPGAs 
  • Arria^® V FPGAs
  • Arria II GX FPGAs 
  • Cyclone^® V FPGAs
  • Cyclone IV GX FPGAs
  • HardCopy^® IV ASICs
• Reference designs for quick and easy design start
  • TI 6482 reference design
  • Serial RapidIO to PCI^TM bridge reference design
• OpenCore Plus evaluation
  • Use the Altera OpenCore Plus evaluation flow to test drive this IP core

Technical Support

For technical support on the RapidIO MegaCore function, please visit the RapidIO MegaCore Support Center. Additional support for the MegaCore function is available in the Altera mySupport online issue tracking system. You can also search for related topics on this function in the Altera Knowledge Database.

A web-based technical training on configuring the RapidIO MegaCore function is also available.

Related Documents

• RapidIO Trade Association