from CAST, Inc.
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Features
- Serial interface engine
- Supports full-speed devices
- Extraction clock and data signals in internal digital phase-locked loop (DPLL)
- Non-return-to-zero-inverted (NRZI) decoding/encoding
- Bit stuffing/stripping
- Cyclic redundancy code (CRC) checking/generation
- Interface for an external transceiver
- Up to 31 configurable endpoints
- Control transfers by endpoint 0
- Bulk, interrupt, and isochronous transfers
- Double buffering for isochronous endpoints
- Programmable double buffering for bulk and interrupt endpoints
- Automatic data retry mechanism
- Data toggle synchronization mechanism
- Suspend and resume power management functions
- Remote wake-up function
- Endpoint buffers RAM interface
- 2 by 1024 bytes FIFO buffer size for isochronous endpoints
- Up to 64 bytes buffer size for each bulk, interrupt, and control endpoints
- Microcontroller interface
- Asynchronous address and data bus interfaces, and read and write control signals (internally synchronized within the CUSB core)
- Interrupt request signals for application microcontroller
- Interrupt vector for autovector interrupts
Description
The CUSB core is a universal serial bus (USB) function controller that provides a USB full-speed function interface that meets the USB Specification, Revision 1.1. The CUSB logic handles byte transfers autonomously and connects the USB interface to a simple read/write parallel interface. The CUSB function can be customized and optimized for a specific application. It contains a set of special function registers that is similar to the Cypress EZ-USB FX chip.
The CUSB function is a microcode-free design developed for reuse in ASIC and programmable logic implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset.
Block Diagram
Device Utilization and Performance
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | ||||||
| Supported Family | Device Tested | I/O Buffers | Utilization | Performance (fMAX) |
Parameter Settings | |
|---|---|---|---|---|---|---|
| LEs(1) | Memory | |||||
| Stratix® II | EP2S15-3 | 49 | 1,046 | 6 M4Ks | 48 MHz | Contact CAST |
| Stratix | EP1S10-5 | 49 | 1,119 | 6 M4Ks | 48 MHz | Contact CAST |
| Cyclone® | EP1C3-6 | 49 | 1,165 | 6 M4Ks | 48 MHz | Contact CAST |
- LE = Logic Element. The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
Deliverables
- Encrypted Licenses
- Post-synthesis Altera hardware description language (AHDL)
- Assignment & configuration files (.acf)
- Symbol file (.sym)
- Include file (.inc)
- Vectors for testing the functionality of the megafunction
- HDL source licenses
- VHDL register transfer level (RTL) source code
- Simulation script
- Synthesis script
- Example CHIP_CUSB design
- Testbench that instantiates:
- Example design CHIP_CUSB
- External endpoint buffers
- Bus/behavioral model of USB host
- Clock generator
- Process that compares your simulation results with the expected results
- A collection of tests that are executed directly by the testbench
Contact Information
For additional information, contact Cast. Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
USA
Tel: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: info@cast-inc.com
URL: www.cast-inc.com
The CUSB megafunction is licensed from Evatronix, S.A.
