USB 2.0 Function Controller
The USB device intellectual property (IP) core is a functional core for devices implementing USB 2.0. It provides all the features necessary to implement a USB device on an SOC design. The USB 2.0 device core acts as the Avalon® slave in Altera’s SOPC builder. Figure 1 shows the block diagram.
Figure 1. SLS USB 2.0 UTMI Block Diagram
Features
The USB 2.0 device core offers the following features:
- Support for both full-speed (12 Mbps) and high-speed (480 Mbps) modes
- Full compliance with USB 2.0 specification
- USB enumeration through hardware with start enable from software
- Support for the USB 2.0 transceiver macrocell interface
- Hardware Abstraction Layer (HAL) driver for the Nios® II embedded processor
- Avalon® interconnect compliant
- Pre-configured for three endpoints
- Control endpoint
- Bulk IN endpoint
- Bulk OUT endpoint
- Optimized for use with Altera's Nios II embedded processor
- Optimized LE count
Deliverables
The USB 2.0 device core includes the following:
- Encrypted core
- Technical documents
- Reference design
- Nios II application (C file)
- HAL driver object code
Contact Information
For additional information, contact:
System Level Solutions India Pvt. Ltd.
9/A, Radhakrishna Colony, Mangalpura Road (Near Ganesh Crossing)
Anand -388001 Gujarat, India
Tel: +910-26920-264661
Email: info@slscorp.com
URL: http://www.slscorp.com
or
System Level Solutions
14708 White Cloud Court
Morgan Hill, CA 95037 USA
Tel: 408 705-2399
Email: info@slscorp.com
URL: http://www.slscorp.com
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