Altera Home Page
Literature Licensing
Buy On-Line Download

  Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line  
  Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature  

 IP Products
   Embedded Processors
       Nios II
          Nios
          32/16-Bit Microprocessors
          8/4-Bit Microprocessors
          Literature
   Interfaces & Peripherals
   DSP
   Communications
  
 About IP
      Designing with IP
      Evaluate and Download IP
      IP Certifications
      System Design
      Request IP
  
 IP Industry Partners
      About AMPP Program
      AMPP Core Partners
  

C68000 Microprocessor

from CAST, Inc.

Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • Control unit
    • 16-bit two levels instruction decoder
    • Three levels instruction queue
  • Instruction & address
    • 55-instructions (87 assembler mnemonics)
    • 14-address modes
  • Supervisor & user modes (independent stack for both modes)
  • User registers
    • Eight 32-bit data registers
    • Eight 32-bit address register
    • 6-bit status register
  • Data format
    • Integer 8, 16, or 32 bits
    • BCD packet
    • Bit
  • Memory interface
    • Independent data & address buses
    • Asynchronous bus control
    • 4-GB address space
    • 31-bit address bus (optional 32-bit)
    • 8-address spaces (used 5)
    • 16-bit data bus
  • Interrupt controller
    • Seven priority levels
    • Virtually an unlimited number of interrupt sources
    • Vectored or auto-vectored interrupt modes
  • Arithmetic-logic unit
    • 8, 16, 32-bit arithmetic operations
    • 8, 16, 32-bit logical operations
    • Boolean manipulations
    • 16 x 16 bit multiplication (sign or unsigned)
    • 32 / 16 bit division (sign or unsigned)
  • M6800 peripherals family synchronous interface
  • Two or three wire bus arbitration interface
  • Operations executions: Same for data or address registers

Block Diagram

Block Diagram

Description

The C68000 is a powerful 16/32-bit microprocessor function that is derived from the MC68000 microprocessor. The C68000 serves interrupts and exceptions, and provides an interface for the M6800 family of peripherals.

The C68000 is a microcode-free design developed for reuse in ASIC and programmable logic device (PLD) implementations. The design is strictly synchronous with a synchronous reset, and no internal tri-states.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Device Speed Grade Utilization Performance
(fMAX)
Parameter Setting
LEs (1) I/O
Stratix™ II EP2S15 -3 4,758 60 29 MHz Contact CAST

Stratix EP1S10

-5 6,560 60 69 MHz Contact CAST
Cyclone® EP1C12 -6 6,152 60 57 MHz Contact CAST
FLEX® EPF10K130 -1 5,823 60 21 MHz Contact CAST
APEX™ II EP2A15 -7 5,507 60 36 MHz Contact CAST
APEX EP20K160E -1 5,496 60 29 MHz Contact CAST

Note:

  1. LEs = logic elements; the LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software

Deliverables

  • Encrypted licenses
    • Post-synthesis AHDL or EDIF
    • Assignment & configuration
    • Symbol file
    • Include file
    • Vectors for testing the functionality of the megafunction
  • HDL source licenses
    • VHDL or Verilog RTL source code
    • Testbench
    • Vectors for testbench
    • Expected results for testbench
    • Simulation script
    • Synthesis script

Contact Information

For additional information, contact CAST, Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Tel: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
URL: www.cast-inc.com

  Please Give Us Feedback