CZ80CPU Processor
Features
- 8-bit instruction decoder control unit
- Arithmetic logic unit (ALU)
- 8-bit arithmetic and logical operations
- 16-bit arithmetic operations
- Boolean manipulations
- Register file unit
- Duplicate set of both general purpose and flag registers
- Two 16-bit index registers
- Interrupt controller
- Three modes of maskable interrupts
- Non-maskable interrupt
- External memory interface
- Can address up to 64 KB of program memory
- Can address up to 64 KB of data memory
- Can address up to 64 KB of input/output devices
- On-megafunction dynamic memory refresh counter
Block Diagram
Figure 1 shows the block diagram for the megafunction.
| Figure 1. Block Diagram |
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Description
The CZ80CPU processor is a fast, single-chip, 8-bit microprocessor megafunction. It is a fully functional 8-bit processor that has the same instruction set as the Zilog Z80. The CZ80CPU processor has a 16-bit address bus capable of direct access of 64 KB of memory space. It has 252 root instructions with four bytes reserved as prefixes, and it accesses an additional 308 instructions.
Programming features contain 208 bits of read/write memory that are accessible to the programmer. The internal registers include an accumulator and six 8-bit registers that can be paired as three 16-bit registers. In addition to general registers, a 16-bit stack pointer, a 16-bit program counter, and two 16-bit index registers are provided.
The CZ80CPU function is a microcode-free design developed for reuse in application-specific integrated circuit (ASIC) and programmable logic device (PLD) implementations. The design is strictly synchronous, it has no internal tri-states and a synchronous reset.
Device Utilization Example
Table 1 lists the typical device utilization results for the CZ80CPU megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Elements (1) |
Memory |
| Cyclone™ 1C6 |
-6 |
3,897 |
- |
82 MHz |
Contact CAST |
| Stratix® 1S10 |
-5 |
3,621 |
- |
99 MHz (2) |
Contact CAST |
| Stratix II 2S15 |
-3 |
3,048 |
- |
138 MHz (2) |
Contact CAST |
Note:
- The logic element count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software.
Deliverables
- Encrypted Licenses
- Post-synthesis Altera hardware description language (AHDL) or electronic data interchange format (EDIF)
- Assignment and configuration
- Symbol file
- Include file
- Graphic design file with sample design
- Vectors for testing the functionality of the megafunction
- HDL Source Licenses
- VHDL or Verilog register transfer level (RTL) source code
- Testbench
- Example testbench wrapper for post-route simulation
- Vectors for testbench
- Simulation script
- Synthesis script
- Expected results for testbench
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677, USA
Phone: +1 (201) 391-8300
Fax: +1 (201) 391-8694
Email: info@cast-inc.com
URL: http://www.cast-inc.com
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