Nios II Processor Family Questions & Answers
These are the questions that are most frequently asked about Altera’s Nios® II family of embedded processors.
General
Device Support & Licensing
System Design & Construction
Nios II Architecture
Software Tools & Middleware
General
What is the Nios II family of embedded processors?
The Nios II embedded processor family is Altera’s second-generation soft embedded processor solution. The Nios II processor cores are 32-bit RISC processors that share a common instruction set architecture and are optimized for use in all of Altera's mainstream FPGA families. Check out the Nios II processor page for details.
What are the specific benefits of the Nios II family of processors?
The Nios II embedded processors offer the ultimate in embedded design versatility. Designers can create the perfect fit solution in terms of processors, peripherals, interfaces, and memory.
The Nios II/e CPU core was specifically designed to be optimized for the lowest possible logic utilization, and, combined with the low-cost FPGA families (such as the CycloneTM II family), offers processor systems for well under $1.00. Learn more about the low-cost benefits of the Nios II processors.
Developers with high-performance requirements will develop with the Nios II/s or Nios II/f processor cores. The Nios II/f core achieves performance of 200 MHz, and can be accelerated much further by offloading compute-intensive software tasks to Nios II custom instructions and hardware accelerators. Additionally, the Nios II C-to-Hardware Acceleration (C2H) Compiler is provided to automate the conversion of this bottleneck software source code into hardware accelerators in the FPGA. Learn more about the high-performance benefits of the Nios II processors.
Finally, the Nios II processors can help you lengthen the life cycle of your products. With productivity tools such as SOPC Builder, the Nios II Integrated Development Environment (IDE), and the Nios II C2H Compiler, combined with a programmable FPGA target device, you can speed your product to market much more quickly than other logic design flows. Using the soft Nios II processors allows designers to conveniently deploy in-field upgrades to software or hardware. Finally, because you own the source files to your custom-built Nios II processor system, your product is immune to component obsolescence. You own the processor, and you protect your investment in the system software.
How many processor cores make up the Nios II processor family?
The Nios II processor is made available as three distinct cores to provide developers with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool.
The Nios II processor family is made up of these cores:
- Nios II/f (fast)–Highest performance, moderate FPGA utilization
- Nios II/s (standard)–High performance, low FPGA utilization
- Nios II/e (economy)–Modest performance, lowest FPGA utilization
What are the benefits of using a soft processor in an FPGA implementation over a hard macro?
By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, developers get a exact-fit solution because they can choose the peripheral, performance, and processor mix that best suits their system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that they can't benefit from the latest process technology. Soft core processors, on the other hand, can migrate immediately to the latest FPGA technology such as the 90-nm-based Stratix® II or Cyclone II device families. Also, standard microprocessor-based solutions are subject to obsolescence issues, whereas Nios II-based solutions resist obsolescence because they are constructed from re-targetable HDL.
How does the Nios II architecture differ from the first-generation Nios processor?
The Nios II processor has a 32-bit RISC instruction-set architecture, whereas the first-generation Nios processor has a 16-bit instruction-set architecture. The Nios II processor reaches new levels of efficiency and performance over the Nios processor core because it consumes much fewer FPGA resources yet quadruples computational performance. The Nios II processor also simplifies the processor selection process by providing a set of pre-optimized cores targeting specific price (logic usage) and performance constraints.
What market segment do the Nios II processors target?
The Nios II processor family can be used in a wide range of applications that require a general-purpose, 32-bit embedded microprocessor.
What is the Nios II C-to-Hardware Acceleration (C2H) Compiler?
The Nios II C2H Compiler is a Nios II productivity tool that automatically accelerates performance-critical software subroutines to significantly improve total system performance. The Nios II C2H Compiler is integrated into the Nios II IDE and is available for free evaluation, but the license file is sold separately.
How can developers benefit by using the Nios II C2H Compiler?
Developers can boost their system’s performance without increasing processor clock frequency by using the FPGA’s logic resources to run segments of their code. Hardware acceleration has the added benefit of improving system performance without making tradeoffs in power consumption.
Device Support & Licensing
Which Altera FPGA families support the Nios II processors?
The Nios II processors are fully supported by the Stratix, Stratix GX, Stratix II, and Cyclone FPGA families. As future FPGA families are released, they will be supported by the Nios II processors, providing customers with even higher levels of processor performance.
Can Nios II processors be implemented in HardCopy structured ASICs?
Yes. For higher volume applications, Altera offers a simple, turnkey migration from FPGA design to HardCopy II structured ASICs. Systems built with Nios II processors are supported and licensed for use in any of Altera's HardCopy structured ASICs.
What is the Nios II licensing model?
Customers who purchase a Nios II development kit receive a perpetual, no-cost license to develop and ship systems using the Nios II embedded processor family and associated peripherals. This royalty-free license applies to designs deployed in Altera FPGAs or HardCopy structured ASICs.
Does Altera offer an ASIC migration path for Nios II processor-based systems?
Yes. An ASIC migration path is available on a case-by-case basis. Customers can contact their Altera representative for complete licensing details.
System Design & Construction
What tools are needed to design with the Nios II embedded processor family?
The Nios II Embedded Design Suite (EDS) represents complete development tool suite for both the creation of Nios II processor-based microcontrollers as well as the programming of the target Nios II systems. The Nios II EDS is included in every Nios II development kit and is also available as a downloadable evaluation edition.
Can multiple Nios II processor cores be implemented in a single FPGA?
Multi-processor systems are completely supported with the Nios II embedded processors. Using the SOPC Builder tool, system designers can add as many Nios II processor cores as required into their system. SOPC Builder automatically generates the HDL design files necessary to properly integrate these cores into the system.
What kind of performance boost should developers expect to get with the Nios II C2H Compiler?
Although performance results can vary sharply depending on several factors (including algorithm implementation and coding style), the Nios II C2H Compiler has been benchmarked at over 40X performance boosts versus a software-only implementation.
What is the Avalon switch fabric?
Most processor systems use bus topologies in which master and slave components share a common system bus. Multiple bus masters must compete for access to the bus and frequently wait for other masters to finish before they can transact with the rest of the system. These bus architectures require designers to spend a large portion of their time verifying that all their peripherals' interfaces work.
The Avalon switch fabric is a custom-built interconnect that is automatically generated by the SOPC Builder design tool and that connects every master and slave port in the system. Because it is a switch fabric and not a systems bus, multiple master ports can operate simultaneously, which dramatically boosts system performance.
Nios II Architecture
What architectural elements are found in Nios II processor cores?
The Nios II processor family provide the basic architectural elements found in most modern 32-bit processors, including:
- 32-bit instruction size
- 32-bit data and address paths
- 32 general-purpose registers
- 32 external interrupt sources
- Configurable instruction cache
- Configurable data cache
- Common interface to up to 256 custom instructions
- Common interface for the integration of custom peripherals
What are custom instructions?
Custom instructions are user-added hardware blocks that augment the arithmetic logic unit (ALU) of a CPU. Nios II processors fully support the use of custom instructions, allowing designers to fine-tune their system hardware to meet performance goals. Users can create up to 256 custom instructions per Nios II processor core used in the system. Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.
Software Tools & Middleware
How do developers build software for a Nios II system?
The Nios II software development tool automatically generates a customized C/C++ run-time environment tailored to the system hardware. The Nios II Integrated Development Environment (IDE) also simplifies project setup by supplying several software templates which can be used as “starter” files in developing custom firmware solutions.
What software debug tools are available for use with Nios II processors?
Altera provides a complete software debugging solution via the Nios II IDE that enables debug to occur via an instruction set simulator (ISS) or directly to system hardware (such as a development board, available in the Nios II development kits). Direct debugging of a Nios II processor system in hardware is enabled through a hardware-assisted debug module. The debug module is rich in features and provides run control, memory examination and modification, hardware breakpoints, data triggers, and processor trace under IDE control.
What third-party software tools are available for the Nios II processors?
Several top embedded software tools providers offer support for the Nios II family of processors, providing operating systems, middleware, software libraries, IDEs, debuggers, co-verification tools, and more. Check out the complete list of up-to-date embedded tools providers.
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