Nios II/e Core—Economy
Altera specifically designed the Nios® II/e "economy" processor core to use the fewest FPGA logic and memory resources, making it the absolute lowest-cost Nios II processor core available. The Nios II/e core has higher performance but is in the same cost class as a typical 8051 architecture, acheiving over 30 DMIPS at up to 200 Mhz, and using fewer than 700 logic elements (LEs).
The core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).
The Nios II/e core features:
- Up to 2 Gbytes of external address space
- JTAG debug module
- Complete systems in fewer than 700 LEs
- Optional debug enhancements
- Up to 256 custom instructions
The Nios II/e core is optimal for cost-sensitive applications, such as those found in the automotive, industrial, and consumer markets. This core is often paired with Altera's low-cost FPGAs and structured ASIC products.
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