Nios II/f Core—Fast
Altera specifically designed the Nios® II/f "fast" processor for high performance. It is optimal for performance-critical applications as well as applications with large amounts of code and/or data, such as systems running a full-featured operating system. With performance over 250 DMIPS and over 200 MHz, the Nios II/f core is in approximately the same performance class as an ARM9TTM core.
The core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).
The Nios II/f core features:
- Separate instruction and data caches (512 bytes to 64 Kbytes)
- Access to up to 2 Gbytes of external address space
- Optional tightly coupled memory for instructions and data
- Six-stage pipeline to achieve maximum DMIPS/MHz
- Single-cycle hardware multiply and barrel shifter
- Optional hardware divide option
- Dynamic branch prediction
- Up to 256 custom instructions and unlimited hardware accelerators
- JTAG debug module
- Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
The Nios II/f core provides additional functionality and performance when targeting Altera® device families with digital signal processing (DSP) blocks. In this case, the Nios II/f core provides hardware multiply circuitry that achieves single-cycle multiply operations. The multiply unit also functions as a single-cycle barrel shifter. The Nios II/f core provides optional divide circuitry that accelerates divide operations.
For the highest performance, implement the Nios II/f core in Altera's highest-performance FPGAs or structured ASIC products.
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