Altera specifically designed the Nios® II/f "fast" processor for high performance. With performance over 300 MIPS* (*Dhrystones 2.1 benchmark), it is optimal for performance-critical applications as well as applications with large amounts of code and/or data, such as running a full-featured operating system.
The Nios II/f core is supported by the Nios II Embedded Design Suite (EDS), including the Eclipse-based Nios II Integrated Development Environment (IDE).
The Nios II/f core features:
- Memory Management Unit (MMU)
- Memory Protection Unit (MPU)
- Advanced exception support
- Separate instruction and data caches (512 bytes to 64 Kbytes)
- Access to up to 2 Gbytes of external address space
- Optional tightly coupled memory for instructions and data
- Six-stage pipeline to achieve maximum MIPS* (*Dhrystones 2.1 benchmark) per MHz
- Single-cycle hardware multiply and barrel shifter
- Hardware divide option
- Dynamic branch prediction
- Up to 256 custom instructions and unlimited hardware accelerators
- JTAG debug module
- Optional JTAG debug module enhancements, including hardware breakpoints, data triggers,
and real-time trace
The Nios II/f core provides additional functionality and performance when targeting Altera® device families with digital signal processing (DSP) blocks. In this case, the Nios II/f core provides hardware multiply circuitry that achieves single-cycle multiply operations. The multiply unit also functions as a single-cycle barrel shifter. The Nios II/f core provides optional divide circuitry that accelerates divide operations.
For the highest performance, implement the Nios II/f core in Altera's highest-performance FPGAs or
HardCopy® ASICs.
