Adveda: Hardware Software Co-Verification
Adveda specializes in the functional verification of software and hardware and helps developers close the system-on-chip (SOC) verification gap by offering ultra-fast, fully integrated simulation and debugging tools. With these tools, both the software and hardware of a SOC can be verified within one environment. Adveda fully supports Altera's Nios® II family of embedded processors.
Adveda's Univers tools greatly simplify the task of debugging and verification by making it possible to simulate multiple CPUs—including bus models, RTL peripherals or C++ models—within one simulation environment.
The Univers tools include features for:
- Combining multiple instruction set simulators (ISS) with VHDL/Verilog code and with C++ code
- Combining CPUs from different manufacturers
- Extremely fast simulation speed
- Extremely detailed level of debug information
- A rich set of features, including breakpoints & interrupt generation
Adveda fully supports the Nios II processors by providing an ISS for the Univers tools. Models for the Avalon® switch fabric and for custom instructions are also available.
The SOPC Builder-generated project file is automatically parsed to configure the Nios II ISS. Custom instructions are fully supported, and timing details (such as cache miss data) are also available. Figure 1 illustrates the Univers tool interaction with Altera's SOPC Builder and Nios II IDE.
Figure 1. Univers Works Seamlessly With Altera's SOPC Builder & Nios II IDE
Additionally, Adveda offers the system-level specification language (SL2) compiler. The SL2 language is used to create instruction set simulators or other models from a high abstraction level description. The SL2 language and compiler are extremely suitable for design exploration purposes. In addition to the SL2 compiler, a testbench generator tool can be provided to automatically verify two different implementations of the same design (ISS model versus Verilog/VHDL, ISS versus ISS, etc.).
Table 1 outlines all of Adveda's tool offerings supporting Nios II processors.
| Table 1. Design Tools Supporting Nios II Processors |
| Design Flow |
Tool Name |
Comments |
| System Level |
| HW/SW Co-Simulation |
Univers COVER |
Hardware/software co-simulation and co-verification tool providing a multi-core development environment supporting CPUs and digital signal processors in combination with Verilog and/or VHDL code. Depending on the ISS (type of CPU), additional items are included such as instruction cache and data cache models, bus models, peripheral models, etc. Univers COVER combines all the features of Univers ISSIM and Univers RTSIM in a single tool. |
| Design Modeling & Exploration |
SL2 Compiler |
The SL2 compiler allows users to fully simulate and explore a non-existing design by providing a high abstraction level description. This description is compiled to C++ code and incorporates all the Univers COVER features. In addition to describing CPUs with caches, branch prediction, etc., the language also fully supports descriptions of peripherals, bus models, etc. |
| Simulation |
HW/SW
Co-simulation |
Univers COVER |
See Univers COVER description above. |
| Software |
Univers ISSIM |
Software simulation environment providing a multi-core development environment. Depending on the ISS (type of CPU), additional items are included such as instruction cache and data cache models, bus models, peripheral models, etc. |
| Hardware |
Univers RTSIM |
Hardware simulation environment for Verilog/VHDL code. This simulator is developed to be able to simulate hardware designs at incredibly fast speeds. |
| Verification |
HW/SW
Co-Simulation |
Univers COVER |
See Univers COVER description above. |
| Software |
Univers ISSIM |
See Univers ISSIM description above. |
| Hardware |
Univers RTSIM |
See Univers RTSIM description above. |
Please contact Adveda for additional information or visit the Adveda website.
Adveda
Finisterelaan 18
5627 TD, Eindhoven
The Netherlands
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