Altera provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon® Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.
The use of Altera’s Qsys and SOPC Builder components, intellectual property cores, and reference designs is governed by, and subject to, the terms and conditions of the Altera Program License Subscription Agreement, the Altera MegaCore Function License Terms and Conditions, and the Altera Hardware Reference Design License Agreement respectively.




