Take your system designs from prototyping to volume production faster with Altera’s innovative design once design flow.
Using Stratix® series FPGA-based seamless prototyping for HardCopy® ASICs allows you to do one design, using one tool, with one methodology, all from one company and then ramp up to production when it makes sense for your application.
Design Once Design Flow Advantage
The HardCopy ASIC design flow (see Table 1) differs from a standard-cell ASIC design in that once the design is complete, you can verify the design in-system and at speed using a companion FPGA. That means you know the hardware and software works in your system, and you are effectively done. Just hand off the netlist to Altera’s HardCopy Design Center for the back-end physical design.
|Table 1. HardCopy Design Flow Advantages|
|HardCopy Design Flow||Advantages|
|ASIC strength, front-end design flow||
|Turnkey back-end process||
Innovative Front-End Design Flow
The HardCopy front-end design flow (see Figure 1) unifies the FPGA and HardCopy designs into one environment with Altera’s Quartus® II software. One design, one register transfer level (RTL), one set of intellectual property (IP), using the Quartus II design software—delivers two implementations: FPGA prototype and HardCopy ASIC.
Figure 1. HardCopy Series Front-End Design Flow
The following highlights the major steps of the HardCopy front-end design flow:
- Start with RTL and timing constraints
- Select a pair of companion FPGA and HardCopy devices
- Synthesize your design with either Quartus II software or third-party EDA synthesis tools
- Run place and route for both FPGA and HardCopy devices
- Run static timing analysis on both devices and verify timing constraints are met
- Verify the design in-system and at speed using a companion FPGA
- Submit design to the HardCopy Design Center
- Receive socket replacement HardCopy ASIC in as little as 10 weeks
Quartus II software gives you a complete development environment, plus capabilities to complete your design processes efficiently (see Table 2).
Note: Altera recommends using the HardCopy first design flow if you are using HardCopy ASICs to increase performance over the FPGA companion device.
|Table 2. Quartus II Features to Facilitate Efficient HardCopy Front-End Design Flow|
|HardCopy Advisor||Provides development guidelines for successful HardCopy design submission to Altera's HardCopy Design Center. It reports the tasks completed and tasks you still need to complete.|
TimeQuest timing analyzer, Altera’s easy-to-use, second-generation, ASIC-strength timing analyzer, offers native support for the Synopsys Design Constraints file format and full scripting capabilities, as well as a complete GUI environment for creating constraints and timing reports.
|Design Assistant||Performs design rule checking to ensure your design operates correctly in the FPGA prototype and in the final HardCopy device implementation.|
|Device Resource Guide||Selection guideline to let you choose the right device.|
For a complete and detailed list of Quartus II features, visit the Quartus II software home page.
Industry-Standard Back-End Design Flow
Altera’s HardCopy Design Center employs a large team of experienced ASIC design engineers to implement the back-end process. Altera's back-end design flow turn-around time leads the ASIC industry. From netlist handoff to design tape out takes one to two months (see Tables 3 and 4).
|Table 3. HardCopy Back-End Design Flow Steps|
|Design Flow Steps||EDA Tools|
|Design for Testability (DFT) Insertion||Altera® Proprietary Tool|
|Test Vector Generation||Synopsys TetraMax ATPG|
|Clock Tree Synthesis (CTS) and Global Signal Insertion||Synopsys Astro|
|Timing and Signal-Integrity Driven Place and Route||Synopsys Astro|
|Post-Layout Parasitic Extraction||Synopsys Star-RCXT|
|Static Timing/Crosstalk/Noise Analysis||Synopsys PrimeTime SI|
|Physical Verification||Synopsys Hercules and Mentor Graphics® Calibre|
|Formal Verification||Cadence Conformal|
|Table 4. Comparison Between Standard-Cell ASIC Flow and Altera HardCopy Flow|
|Typical Standard-Cell, Back-End Flow||Altera HardCopy Back-End Flow|
|Verification after netlist handoff, causing:
||Design fully verified in-system with an FPGA:
|Result: Schedule delays||Result: Maintain schedule with no surprises|