Structured ASIC Design Flow
Altera delivers the only seamless migration from high-performance Stratix® series FPGAs to low power, pin-compatible, and low-cost HardCopy® structured ASICs.
Design Flow Advantage
Design HardCopy structured ASICs the way you design FPGAs. You can simulate and synthesize the register transfer level (RTL) code, place and route the design netlist, perform timing analysis, and close timing requirements.
The HardCopy structured ASIC design flow (see Table 1) differs from a standard-cell ASIC design in that once the design is complete, you can verify the design in-system and at speed using a companion FPGA. That means you know the design works in your system, and you are effectively done. Hand off the netlist to Altera’s HardCopy Design Center for back-end physical design.
| Table 1. HardCopy Design Flow Advantages |
| HardCopy Design Flow |
Advantages |
| Full in-system verification using an FPGA |
- Reduce risk of design re-spin
- Enable early software co-design
- Lowest total development cost
|
| FPGA-like, front-end design flow |
- Low-cost design environment compared to other structured ASICs or standard-cell ASIC design flows
- Minimal design tools and methodology learning curve
|
| Seamless migration |
- No board re-spin needed because of the same intellectual property (IP) and pin-out for both FPGA and HardCopy devices
- Flexible production choice using either FPGA or HardCopy devices, depending on volume and product life
- Enable fast time-to-market using an FPGA for early production
|
Unified Front-End Design Flow
The HardCopy front-end design flow (see Figure 1) unifies the FPGA and HardCopy designs into one environment with Altera’s Quartus® II software.
Figure 1. HardCopy Series Front-End Design Flow
The following highlights the major steps of the HardCopy front-end design flow:
- Start with RTL and timing constraints
- Select a pair of companion FPGA and HardCopy devices
- Synthesize your design with either Quartus II software or third-party EDA synthesis tools
- Run place and route for both FPGA and HardCopy devices
- Run static timing analysis on both devices and verify timing constraints are met
- Verify the design in-system and at speed using a companion FPGA
- Submit design to the HardCopy Design Center
- Receive socket replacement HardCopy structured ASIC in as little as 10 weeks
Quartus II software gives you a complete development environment, plus capabilities to complete your design processes efficiently (see Table 2).
| Table 2. Quartus II Features to Facilitate Efficient HardCopy Front-End Design Flow |
| Feature |
Description |
| HardCopy II Advisor |
Provides development guidelines for successful HardCopy II design submission to Altera's HardCopy Design Center. It reports the tasks completed and tasks you still need to complete. |
| Choice of Timing Tool |
You can use the TimeQuest timing analyzer or classic timing analyzer to perform static timing analysis of HardCopy design based on cell placement and global route. The TimeQuest timing analyzer is an ASIC-strength tool supporting the industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology. |
| Incremental Compilation |
Reduces design compilation times up to 70 percent and improves timing closure by allowing you to target design optimization options to individual design partitions while preserving performance in other partitions. Supports team-based design environment. |
| Design Assistant |
Performs design rule checking to ensure your design operates correctly in the FPGA prototype and in the final HardCopy device implementation. |
| Device Resource Guide |
Selection guideline to let you choose the right device. |
For a complete and detailed list of Quartus II features, visit the Quartus II software home page.
Industry-Standard, Back-End Design Flow
Altera’s HardCopy Design Center employs a large team of experienced ASIC design engineers to implement the back-end process. Altera's back-end design flow turn-around time leads the ASIC industry. From netlist handoff to design tape out takes only one to two months, depending on design complexity (see Tables 3 and 4).
| Table 3. HardCopy Back-End Design Flow Steps |
| Design Flow Steps |
EDA Tools |
| Design for Testability (DFT) Insertion |
Synopsys DFT Compiler |
| Test Vector Generation |
Synopsys TetraMax ATPG |
| Clock Tree Synthesis (CTS) and Global Signal Insertion |
Synopsys Astro |
| Timing and Signal-Integrity Driven Place and Route |
Synopsys Astro |
| Post-Layout Parasitic Extraction |
Synopsys Star-RCXT |
| Static Timing/Crosstalk/Noise Analysis |
Synopsys PrimeTime SI |
| Physical Verification |
Synopsys Hercules and Mentor Graphics® Calibre |
| Formal Verification |
Cadence Conformal |
| Table 4. Comparison Between Standard-Cell ASIC Flow and Altera HardCopy Flow |
| Typical Standard-Cell, Back-End Flow |
Altera® HardCopy Back-End Flow |
Verification after netlist handoff, causing:
- Concern for low-level semiconductor test details
- Multiple verification cycles
- Functional engineering change orders (ECOs) and place-and-route merges
|
Design fully verified in-system with an FPGA:
- Test insertion and pattern generation is transparent
- Eliminates functional ECOs
- Ensures predictable back-end turn-around time
|
| Result: Schedule delays |
Result: Maintain schedule with no surprises |
Summary
Altera’s unique HardCopy structured ASIC design flow is low risk, low cost, easy to use, and easy to adapt. Use the same industry-proven toolset as you use for Altera® FPGAs. You get turnkey, guaranteed seamless migration from Altera’s FPGA to HardCopy device, plus fast and predictable design completion. The HardCopy structured ASIC solution is the true alternative to the long design time, high cost, and high risk associated with standard-cell ASICs.
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