Easiest-to-Use Design Software for CPLDs
Altera’s Quartus® II Subscription Edition software and the no-cost Quartus II Web Edition software support MAX® II CPLDs with an easy-to-use and comprehensive design environment that can take CPLD design projects from start to finish (see Figure 1). Quartus II Subscription Edition and Quartus II Web Edition software also integrate seamlessly with all leading third-party synthesis and simulation tools.
Figure 1. Quartus II Software CPLD Design Flow

Quartus II Advantages for MAX+PLUS II Users
The Quartus II software is the highest performance and easiest-to-use software available for CPLD designs. With a built-in MAX+PLUS® II look-and-feel option (see Figure 2), MAX+PLUS II software users can get the full benefits of the advanced features and performance of Quartus II software without having to learn a new interface.
Figure 2. Quartus II Software's Built-In MAX+PLUS II Look-&-Feel Option

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In addition to the MAX+PLUS II software interface option, the Quartus II software offers some important advantages over the MAX+PLUS II software (see Table 1).
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Table 1. Quartus II Advantages Over MAX+PLUS II Software
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Design Method
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Supported Features
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Device Support
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Supports the MAX II CPLD family, including the MAX IIZ variant, in addition to the MAX 3000A, 7000AE, MAX 7000B, and MAX 7000S families that are supported by the MAX+PLUS II software
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Supports the latest FPGAs such as Cyclone®, Stratix®, and ArriaTM GX FPGAs
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Performance
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Offers better performance than the MAX+PLUS II software version 10.2 for MAX 3000A, MAX 7000AE, MAX 7000B, and MAX 7000S designs
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Synthesis
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Integrates register transfer level (RTL) synthesis support for the latest VHDL and Verilog language standards in addition to AHDL support
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RTL viewer provides a graphical representation of VHDL or Verilog designs before synthesis and design implementation (in the Quartus II Subscription Edition software only)
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Supports all leading third-party synthesis flows
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Advanced Features
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Advanced features for supporting MAX II CPLDs and the latest FPGA families
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PowerGauge power analysis (includes support for MAX IIZ CPLDs)
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LogicLock™ block-based design flow (now included for MAX II designs)
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SOPC Builder
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Compilation
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Verification features
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Last-minute design change support (ECO support)
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Chip planner
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Incremental fitting
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