FPGA Design Flow
Altera’s Quartus® II software leads the industry as the most comprehensive environment available for FPGA designs, delivering unmatched performance, efficiency, and ease-of-use. For detailed FPGA design flow information, see:
The Quartus II software now features unique advantages in design flow methodology, system design, timing-closure methodology, in-system verification technology, and third-party EDA support. Highlights of Quartus II software FPGA design flow features are provided below. Figure 1 shows a high-level example of some of the Quartus II software FPGA design flow options. Some steps can be performed in a different order than shown in Figure 1.
Figure 1. FPGA Design Flow
Note:
- RTL = register transfer level
FPGA Design Flow Methodology
Advantages of the Quartus II software’s powerful yet easy-to-use FPGA design flow are listed below:
Up-Front I/O Assignment and Validation: Quartus II software accelerates FPGA design productivity and improves time-to-market and ease-of-use because it performs I/O assignment and validation (PDF) up front (even before design modules are available). This enables printed circuit board (PCB) layout to begin earlier in the design process.
Quartus II Integrated Synthesis & Support for Third-Party Synthesis: Quartus II software includes a comprehensive integrated synthesis solution (PDF) and advanced integration with leading third-party synthesis software from Mentor Graphics®, Synopsys, and Synplicity.
Memory Compiler: Quartus II software users can select and configure memory from an easy-to-use graphical user interface (GUI) or infer memory directly in VHDL or Verilog source code. The memory compiler supports "what-if" analysis by dynamically producing waveform displays of memory structure operation based on user parameterization.
Scripting Support: Quartus II software allows both GUI-based and scripting-based design techniques. Quartus II software is the first FPGA and structured ASIC implementation tool from a programmable logic device (PLD) vendor to support the industry-standard tool command language (Tcl) scripting interface (PDF).
System Design Technology
Altera’s Quartus II software is the first design environment that supports intellectual property (IP)-based system design—including complete and automated system definition and implementation—without requiring lower- level hardware description language (HDL) or schematics. This capability enables you to turn your concepts into working systems in minutes. The Quartus II system design tools include those tools listed below.
SOPC Builder: This system development tool automates adding, parameterizing, and linking IP cores—including embedded processors, coprocessors, peripherals, memories, and user-defined logic—without requiring lower-level HDL or schematics.
DSP Builder: The DSP Builder tool shortens digital signal processing (DSP) design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment.
Off-the-Shelf IP Cores: The popular Nios® II embedded processor and parameterized IP blocks from Altera and Altera Megafunction Partners Program (AMPPSM) partners have been rigorously tested and optimized for the highest performance in Altera® devices.
Timing-Closure Methodology
Empowered with industry-leading timing-closure methodologies, Quartus II software delivers unmatched capability for you to quickly satisfy design timing requirements. Altera is the first programmable logic supplier to develop and deliver a comprehensive set of timing-closure methodologies as an integrated part of its existing tools suite at no additional cost.
Incremental Compilation: An industry first, Quartus II incremental compilation feature reduces design compilation times up to 70 percent and improves timing closure by allowing you to target design optimization options to individual design partitions and preserve performance in other partitions by leaving them untouched.
Physical Synthesis: The FPGA industry's only integrated physical synthesis technology (PDF) improves design performance without user intervention.
Design Space Explorer Script: The design space explorer methodology (PDF) increases performance and saves engineering time by applying combinations of Quartus II software settings to automatically seek out optimum performance . It also supports distributed environments where multiple computers can run simultaneous compilations using different optimization settings.
Timing Closure Floorplan Editor: The timing closure floorplan editor methodology (PDF) improves analysis of timing data in the floorplan.
Chip Planner: The Chip Planner reduces verification time (while maintaining timing closure) by enabling small, post-place-and-route design changes to be implemented in minutes.
Registered Transfer Level (RTL) and Technology Map Viewers: The Netlist Viewers (PDF) provide a schematic representation of designs you can use to analyze a design’s structure before further behavioral simulation, synthesis, and place-and-route steps are performed. Designs can now be debugged in Quartus II software after the synthesis and place-and-route steps at a detailed level by viewing a logical representation of the design implementations mapped into Altera device primitives, including detailed timing information.
Verification Solution
In addition to integrating with all of the leading third-party EDA verification tools and methodologies, Quartus II software also provides the following features:
TimeQuest Timing Analyzer: TimeQuest is a next-generation, ASIC-strength timing analyzer supporting the industry-standard Synopsys Design Constraints (SDC)-based timing analysis methodology. TimeQuest Timing Analyzer enables you to create, manage, and analyze complex timing constraints, and to quickly perform advanced timing verification
Advanced Multi-Clock Timing-Analysis Capabilities: The advanced multi-clock timing-analysis (PDF) capabilities allow you to determine the speed-critical and performance-limiting paths in a design and optimize critical timing paths.
PowerPlay Power Analysis and Optimization Technology: PowerPlay technology enables you to accurately analyze and optimize both dynamic and static power consumption from design concept through implementation.
Chip Planner: The Chip Planner implements incremental design changes in-system in just minutes.
ModelSim-Altera: ModelSim-Altera is a version of the popular Mentor Graphics ModelSim® software supporting only Altera devices. This software is included with universal edition Altera development software packages.
Third-Party Solutions: Altera works closely with third-party verification tool vendors to provide access for all of the latest FPGA verification flows and methodologies including functional and timing simulation, static timing analysis, board-level simulation, signal integrity analysis, and formal verification.
In-System Verification Suite
SignalProbe Routing: The Signal Probe feature (PDF) incrementally routes an internal node to an unused or reserved pin for analysis with an external scope or logic analyzer.
The SignalTap II Embedded Logic Analyzer: The SignalTap® II logic analyzer supports the most channels, fastest clock speeds, and the largest sample depths available. It also features the most advanced triggering capabilities available in an FPGA-embedded logic analyzer.
In-System Updating of Memory and Constants: You can now easily perform “what if” type experiments in just seconds with in-system updating of memory and constants (PDF). Quartus II software enables FPGA memory and design constants to be updated in-system without recompiling a design or reconfiguring the rest of the FPGA.
Third-Party EDA Support
Altera and its EDA partners collaborate to deliver seamless integration between the Quartus II software and third-party EDA software for synthesis, functional and timing simulation, static timing analysis, board-level simulation, signal integrity analysis, and formal verification.
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