Combining the Open Computing Language (OpenCL™) programming model with Altera’s massively parallel FPGA architecture provides a powerful solution for system acceleration. The Altera® SDK for OpenCL* provides a design environment for you to easily implement OpenCL applications on FPGAs.
Benefits of OpenCL on FPGAs
Are You a Software Developer? How Can You Benefit from OpenCL on FPGAs?
- You get higher performance and a power-efficient solution
- Increase your performance by offloading performance-intensive functions from the host processor in an FPGA.
- Achieve significantly lower power with high performance compared to other hardware alternatives. With the FPGA’s fine-grain architecture, the Altera SDK for OpenCL generates only the logic you need to deliver with as low as 1/5 of the power of hardware alternatives.
- You have a programmer-friendly solution to target FPGAs
- As a software programmer, you can now target FPGAs using OpenCL without learning a hardware description language (HDL).
Design for Higher Performance and Lower Power with OpenCL on Altera FPGAs (for Software Developers)
Watch this webcast to understand:
Are You an Embedded or DSP Designer? How Can You Benefit from OpenCL on FPGAs?
- You get faster time to market
- Achieve significantly faster time to market compared to the traditional FPGA design flow.
- Describe your algorithms using the OpenCL C (based on ANSI C) parallel programming language instead of the traditional low-level HDL.
- Perform design exploration quickly by staying at a higher level of design abstraction.
- Obsolescence-proof your designs as you can retarget your OpenCL C code to current and future FPGAs.
- Generate an FPGA implementation of your OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs
Watch this webcast to understand:
The growing need for higher performance and faster time to market through parallel programming in software is seen in many markets, including the Computer & Storage, Military, Medical, and Broadcast markets.
- Implementing FPGA Design with the OpenCL Standard (PDF)
- Fractal Video Compression in OpenCL: An Evaluation of CPUs, GPUs, and FPGAs as Acceleration Platforms (PDF)
- Using OpenCL to Evaluate the Efficiency of CPUs, GPUs, and FPGAs for Information Filtering (PDF)
- 40Gbit AES Encryption Using OpenCL and FPGAs (PDF)
|Unified Heterogeneous Programmability of OpenCL
Watch how OpenCL provides a unified platform for heterogeneous computing. In this demo, we retarget NVIDIA code written for a GPU to a Stratix® V FPGA.
Accelerating Algorithm Performance with OpenCL by Offloading to an FPGA
|Instructor-led training||OpenCL for Altera FPGAs Training (four days) by Acceleware – available now!
Learn how to write and optimize OpenCL applications for Altera FPGAs. You will also learn how to achieve high performance by taking advantage of the heterogeneous nature of OpenCL and the massively parallel capabilities of Altera FPGAs. The training includes innovative hands-on exercises and a series of progressive lectures. Small class sizes maximize learning and ensure a personal educational experience.
|Local workshop or training class||Parallel Computing with OpenCL Workshop (one day)
Get an overview of the OpenCL standard and the OpenCL for FPGA design flow. Workshop includes hands-on exercises.
|Free online classes||
Introduction to Parallel Computing with OpenCL (30 minutes)
Writing OpenCL Programs for Altera FPGAs (1 hour)
Running OpenCL on Altera FPGAs (30 minutes)
Frequently Asked Questions
The OpenCL standard is the first open, royalty-free, unified programming model for accelerating algorithms on heterogeneous systems. OpenCL allows the use of a C-based language for developing code across different platforms ̶ from CPUs, GPUs, digital signal processing (DSP) devices, and FPGAs.
OpenCL is a programming model for software engineers and a methodology for system architects or engineering management. It is based on standard ANSI C (C99) with extensions to add parallelism. OpenCL also includes an API, a standard interface for the CPU to communicate with the hardware accelerator. A key benefit of OpenCL is that it is a portable open, royalty-free standard, which is a key differentiator versus proprietary programming models.
The OpenCL model allows any CPU to communicate with any hardware accelerator. It’s up to the individual CPU and hardware accelerator vendors to abstract away vendor specific implementation to meet conformance testing. The Altera SDK for OpenCL v13.0 is conformant with the OpenCL 1.0 standard. For more information on the OpenCL 1.0 standard, refer to the Khronos specification.
OpenCL is supported by many vendors who are part of the Khronos group. For more information, visit http://www.khronos.org/opencl/
For an overview on OpenCL for Altera FPGAs, view the Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs webcast.
An OpenCL application consists of a host program and kernel code. The host program is pure software written in standard C. Any standard C compiler can compile this host program, for example, Microsoft Visual studio or GCC. The Altera SDK for OpenCL provides a compiler to compile your OpenCL code to HDL.The compiler takes the kernel code and generates for you a programming file. This programming file is then downloaded into the FPGA so you can run your hardware acceleration. The OpenCL compiler generates custom hardware for your kernel.
The Altera SDK for OpenCL supports a variety of boards. For more information about our preferred board partners and OpenCL certified boards, please visit the Altera’s Preferred Board Partner Program for OpenCL page.
Get started now! Altera is working with several board partners to roll out support for the Altera SDK for OpenCL. For more information or to buy a board from one of our preferred OpenCL board partners, visit the Altera’s Preferred Board Partner Program for OpenCL page. The Altera SDK for OpenCL is included with OpenCL boards from Altera’s preferred partners.
- Buy a board from one of our preferred partners
- Download the Altera SDK for OpenCL
- Take an OpenCL training
- Register for updates on Altera’s OpenCL solution for FPGAs
For additional information on OpenCL, refer to the following:
- The OpenCL Specification Version 1.0 (PDF)
- Altera SDK for OpenCL Getting Started Guide (PDF)
- Altera SDK for OpenCL Programming Guide (PDF)
- Altera SDK for OpenCL Optimization Guide (PDF)
- Join the Altera Forum for OpenCL
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and is expected to pass the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.