The Altera® SDK for Open Computing Language (OpenCLTM) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, or prototype the accelerator kernel on a virtual FPGA fabric in minutes, pushing the longer compile time to the end when you are pleased with your kernel code results.
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OpenCL on FPGAs for GPU Programmers
Learn about the benefits of using Altera FPGAs to accelerate your high-performance designs, and discover how executing and optimizing OpenCL kernels are done on FPGAs versus GPUs.
Demonstrations and Webcasts
Create Your Custom OpenCL Board or Purchase from an Altera Preferred Board Vendor
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The OpenCL standard is the first open, royalty-free, unified programming model for accelerating algorithms on heterogeneous systems. OpenCL allows the use of a C-based programming language for developing code across different platforms such as CPUs, GPUs, digital signal processors (DSP), and FPGAs.
OpenCL is a programming model for software engineers and a methodology for system architects. It is based on standard ANSI C (C99) with extensions to extract parallelism. OpenCL also includes an application program interface (API) for the host to communicate with the hardware accelerator, traditionally over PCI Express®, or one kernel to communicate with another without host interaction. In addition to this, Altera provides, as a vendor extension, an I/O Channel API to stream data into a kernel directly from a streaming I/O interface such as 10Gb Ethernet. A key benefit of OpenCL is that it is a portable open, royalty-free standard, which is a key differentiator versus proprietary programming models.
In the OpenCL model, the user schedules tasks to command queues, of which there is at least one for each device. The OpenCL run-time then breaks the data-parallel tasks into pieces and sends them to the processing elements in the device. This is the method for a host to communicate with any hardware accelerator. It is up to the individual hardware accelerator vendors to abstract away the vendor-specific implementation. The Altera SDK for OpenCL v14.0 does this and conforms to the OpenCL 1.0 standard.
For more information on the OpenCL 1.0 standard, refer to The OpenCL Specification (PDF) by Khronos.
OpenCL is supported by many vendors who are part of the Khronos group. For more information, visit http://www.khronos.org/opencl/
For an overview on OpenCL for Altera FPGAs, view the Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs webcast.
The Altera SDK for OpenCL allows the easy implementation of applications onto FPGAs by abstracting away the complexities of FPGA design, allowing software programmers to write hardware-accelerated kernel functions in OpenCL C, an ANSI C-based language with additional OpenCL constructs. As part of our SDK we provide a suite of tools to further resemble the fast development flow of software programmers, including:
- An emulator to step through the code on an x86 and ensure it is functionally correct
- A detailed optimization report to understand the load and store inner loop dependencies
- A rapid prototyping tool to further push off the longer compile times associated with building an FPGA and run the kernel code on a prebuilt FPGA template
- A profiler that shows performance insight into the kernel to ensure proper memory coalescence and stall free hardware pipelines
- An OpenCL compiler capable of performing over 300 optimizations on the kernel code and producing the entire FPGA image in one step
The Altera SDK for OpenCL is in full production release, making Altera the first FPGA company to have a solution that conforms to the OpenCL specification. The Altera SDK for OpenCL supports a variety of host CPUs, including the embedded ARM® Cortex®-A9 processor cores in SoC devices, the IBM Power Series processors, and a standard x86 CPU. The Altera SDK for OpenCL supports scalable solutions on multiple FPGAs and multiple boards as well as a variety of memory targets, such as DDR SDRAM for sequential memory accesses, QDR SRAM for random memory accesses, or internal FPGA memory for low-latency memory access. Half-precision as well as single- and double-precision floating point is also supported.
For additional information on OpenCL:
Purchase our Altera SDK for OpenCL
Purchase a board and download the Board Support Package for that board
Download and run a reference design
Download the XML file for a board and start developing your algorithm
- How to Do Reductions
- Being Careful with Memory Access Part 1
- Being Careful with Memory Access Part 2
- OpenCL on FPGAs for GPU Programmers (PDF)
- FPGA Acceleration of Multifunction Printer Image Processing Using OpenCL (PDF)
- Implementing FPGA Design with the OpenCL Standard (PDF)
- Fractal Video Compression in OpenCL: An Evaluation of CPUs, GPUs, and FPGAs as Acceleration Platforms (PDF)
- Using OpenCL to Evaluate the Efficiency of CPUs, GPUs, and FPGAs for Information Filtering (PDF)
- 40Gbit AES Encryption Using OpenCL and FPGAs (PDF)
- Is Altera’s OpenCL SDK ready for business? (PDF)
- FPGA Acceleration of Lattice Boltzmann using OpenCL (PDF)
- Characterization of OpenCL on a Scalable FPGA Architecture (PDF)
- Optimizing OpenCL for Altera FPGAs
- OpenCL Implementation of Gzip on Field-Programmable Gate-Arrays
- Energy-Efficient FPGA Implementation for Binomial Option Pricing Using OpenCL
- From OpenCL to Gates: The FFT
- From OpenCL to High-Performance Hardware on FPGAs
- OpenCL for FPGAs: Prototyping a Compiler (PDF)
- Improving FPGA Designer Productivity Using OpenCL (PDF)
- OpenCL for FPGA - Bringing FPGAs to the (relative) masses Part 1
Achieve Power Efficiency in a Single Chip Solution Using OpenCL on Our SoCs
|Unified Heterogeneous Programmability of OpenCL
Watch how OpenCL provides a unified platform for heterogeneous computing. In this demo, we retarget NVIDIA code written for a GPU to a Stratix® V FPGA.
|Accelerating Algorithm Performance with OpenCL by Offloading to an FPGA
Watch how OpenCL accelerates the performance of the Mandelbrot algorithm ̶ an iterative, arithmetically intensive floating-point algorithm.
Optimization and Emulation Flow in Altera SDK for OpenCL
|Rapid Prototyping with the Altera SDK for OpenCL
See how you can prototype your FPGA-accelerated application using the Altera SDK for OpenCL.
An Introduction to OpenCL for Altera FPGAs, (25 minutes)
Watch this webcast to understand:
|Instructor-led training||Parallel Computing with OpenCL Workshop (1 day)
Get an overview of parallel computing, the OpenCL standard and the OpenCL for FPGA design flow. The focus on the class is not on writing kernels, but rather going over the FPGA specific portion of creating an OpenCL environment for hardware acceleration. The workshop includes hands-on exercises and is taught by Altera application engineers who are dedicated trainers.
Optimizing OpenCL for Altera FPGAs (1 day)
This class focuses on writing kernel functions that are optimized for Altera FPGAs. The workshop includes hands-on exercises and is taught by Altera application engineers who are dedicated trainers.
OpenCL for Altera FPGAs Training (4 days) by Acceleware
Learn how to write and optimize OpenCL applications for Altera FPGAs. You will also learn how to achieve high performance by taking advantage of the heterogeneous nature of OpenCL and the massively parallel capabilities of Altera FPGAs. The training includes innovative hands-on exercises and a series of progressive lectures. Small class sizes maximize learning and ensure a personal educational experience.
|Free online classes||
Introduction to Parallel Computing with OpenCL (30 minutes)
Writing OpenCL Programs for Altera FPGAs (1 hour)
Running OpenCL on Altera FPGAs (30 minutes)
Single-Threaded vs. Multi-Threaded Kernels (17 minutes)
Building Custom Platforms for Altera SDK for OpenCL (1 hour)