EDA ACCESS Partner Profiles: TransEDA
Overview
TransEDA delivers a complete solution for verification measurement through coverage analysis. Unique functionalities such as coverability analysis, specification coverage with impact analysis, and automatic bus protocol checking, enhance traditional code coverage, test suite optimization, HDL rule checking, and static assertion checking capabilities to form an integrated Verification Closure Management solution. Other products include verification intellectual property (IP) with bus-based, system-level test automation and transistor-level functional abstraction.
TransEDA’s verification tools support SystemVerilog, Verilog HDL, and VHDL designs as well as Accellera’s PSL formal property language. Running on UNIX, Linux, and Windows platforms, the tools seamlessly integrate with leading HDL simulators including those from Cadence, Mentor Graphics®, and Synopsys and hardware-assisted verification platforms from Cadence/Verisity, Mentor Graphics, and EVE.
TransEDA has offices in North America, Europe, and Japan, plus local representatives in China, India, Korea, Singapore, and Taiwan. For more information, visit www.transeda.com.
Tools
Table 1 lists design tools supporting Altera® devices.
| Table 1. Design Tools Supporting Altera Devices |
| Design Flow |
Tool Name |
Comments |
| Design Entry |
| Rule Checker |
VN-Check |
VN-Check is a configurable HDL rule checker that analyzes VHDL, Verilog HDL, and SystemVerilog designs to provide concise reports on problematic areas. You can configure VN-Check's rules at a very detailed level to match the design flow requirements helping to speed verification, enable design-for-reuse and provide valuable feedback to HDL designers. You can organize rules into rule-sets and share them among design groups to enforce consistent HDL coding style. Predefined rule-sets exist to check for design issues such as design style, synthesizability, testability, documentation naming conventions, and FPGA design compliance. Optionally, you can use a collection of advanced rules that perform deeper formal analysis of design consistency. |
| Verification |
| Code Coverage |
VN-Cover |
VN-Cover is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes the most comprehensive set of metrics in the industry, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, and arc and path. In addition, the tool offers advanced features such as deglitch and the coverability analysis option, aimed at increasing measured coverage accuracy and speeding up convergence to sign-off coverage criteria. VN-Cover seamlessly works with all leading simulators to measure code coverage on VHDL, Verilog HDL, and mixed-language designs. It is the only vendor-neutral coverage tool that works across simulators, languages, and platforms, and can be used within hardware-accelerated verification environments. |
|
Protocol Checker
|
imPROVE-HPK |
imPROVE-HPK is a formal verification tool dedicated to the verification of hardware FPGA and ASIC designs based on standard protocol interfaces (such as OCP, AHB, APB, AXI, etc.). imPROVE-HPK automatically creates a complete protocol environment for the design, and then subsequently checks each of the protocol properties (including functional performance analysis properties) and coverage scenarios. It either proves that the protocol property is true with 100% coverage, or computes a violation test-sequence in either VCD format or as a Verilog HDL/VHDL testbench for easy debugging. |
|
Property Checker
|
| imPROVE-HDL |
imPROVE-HDL is a static property checker that increases productivity of SoC verification by complementing traditional simulation. Unlike dynamic assertion checking or random test generation techniques, it performs exhaustive debugging of register transfer level (RTL) models without using test benches. imPROVE-HDL finds the difficult-to-reach bugs hidden in complex protocol or control implementations, and helps identify and fix ambiguities in FPGA's and ASIC's specifications. imPROVE-HDL easily fits into assertion-based verification (ABV) methodologies and dramatically reduces design verification time while increasing overall confidence. |
Contact Information
For additional information, contact TransEDA at:
Europe
Black Horse House,
Leigh Road, Eastleigh,
Hampshire, SO50 9FH
Tel: +44 (0)23 8068 3500
Fax: +44 (0)23 8065 0805
E-Mail: info@transeda.com
North America
TransEDA, Inc.
16795 Lark Avenue, Suite 102,
Los Gatos, CA 95032
Tel: +1 (408) 335 1300
Fax: +1 (408) 335 1319
E-Mail: info@transeda.com
Japan & Asia
Nihon TransEDA KK
1024 Silk Building,
1 Yamashita-cho, Naka-ku,
Yokohama 231-0023
Tel: +81 (0)45 227 6201
Fax: +81 (0)45 227 6202
E-Mail: salesjapan@transeda.com
|
Literature
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