Design Entry
Design entry tools support design entry and rules check. Table 1 lists design entry tools and their descriptions from several vendors.
| Table 1. Design Entry and Rules Check |
| EDA Vendor |
Tool Name |
Description |
| Aldec |
Active HDL |
VHDL
Verilog
C/C++
EDIF |
| Altium |
nVisage |
Design capture |
| Protel |
Schematic entry |
| Celoxica |
Nexus PDK |
System-level co-verification |
| HDL Works |
Ease/Eale |
Graphical/test entry |
| Mentor Graphics® |
FPGA Advantage |
Complete integrated design environment for FPGAs |
| Visual Elite |
High-level C/C++
SystemC functional modeling and verification |
| SynaptiCAD |
VeriLogger Pro |
Design and verification environment |
| Synopsys |
LEDA |
Coding and design checker |
| Synplicity |
Synplify |
Logic synthesis |
| Synplify Pro |
Logic synthesis |
|
 |
|
Literature
> 
