FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

EDA Partners

Home > Products > Design Software > EDA Partners
Access Program The Altera® Commitment to Cooperative Engineering Solutions (ACCESS) program ensures that you have a complete design solution in designing, verifying, and integrating Altera FPGAs and HardCopy® ASICs into your systems.

List of ACCESS program partner solutions by:

  • System-level design
  • Design creation
  • Synthesis
  • Simulation
  • Verification
  • Board-level design
  • ASIC prototyping
ACCESS Program Partner
System- Level Design
Design Creation
Synthesis
Simulation
Verification
Board-Level Design
ASIC Prototyping

Aldec, Inc.

 

 

 

Check

Check

 

 

Agilent Technologies

 

 

 

 

 

Check

 

Agnisys Technology Pvt Ltd

 Check

           

Altium

Check

 

 

 

 

Check

 

Auspy Development Inc.

 

 

 

 

 

 

Check

Blue Pearl

 

 

 

 

Check

 

 

Bluespec

Check

 

 

 

 

 

 

Cadence Design Systems,Inc.

Check

 

 

Check

Check

Check

 

DAFCA

 

 

 

 

Check

 

 

EMA Design Automation

 

 

 

 

Check

 

 

FishTail

 

 

 

 

Check

 

 

GateRocket

 

 

 

 

Check

 

 

Impulse Accelerated
Technologies

Check

 

 

 

 

 

 

Mentor Graphics

Check

Check

Check

Check

Check

Check

 

PDTi

Check

 

 

 

 

 

 

Poseidon Design Systems

Check

 

 

 

 

 

 

Real Intent

 

 

 

 

Check

 

 

Simucad Design Automation

 

 

 

Check

 

 

 

Signal Integrity Software, Inc. (SiSoft)

 

 

 

 

 

Check

 

Symphony EDA

 

 

 

Check

 

 

 

SynaptiCAD

Check

 

 

Check

Check

 

 

Synopsys

Check

 

Check

Check

Check

Check 

Check

Taray, Inc

 

 

 

 

 

Check

 

Temento Systems

 

 

 

 

Check

 

 

TransEDA

 

 

 

 

Check

 

 

Zuken

 

 

 

 

 

 Check

 

 

Back to Top

Table 1. System-Level Design
EDA Vendor Product Name Design Solution

Altium

Altium Designer

High-level design tool

Agnisys Technology Pvt Ltd IDesignSpec Register map management

Bluespec

Bluespec Compiler

High-level synthesis

Cadence Design Systems,Inc.

C-to-Silicon Compiler

High-level synthesis

Impulse Accelerated Technologies

ImpulseC CoDeveloper

High-level synthesis and simulation

Mentor Graphics

Catapult-C

High-level synthesis

PDTi

SpectaReg

Register map management

Poseidon Design Systems

Triton Tuner

System-level simulation

Triton Builder

High-level synthesis

SynaptiCAD

TestBencher Pro

High-level design tool

Synopsys

Synplify DSP

High-level design tool

Back to Top

Table 2. Design Creation
EDA Vendor Product Name Design Solution

Mentor Graphics

HDL Designer

Project management, design entry and analysis tool

Back to Top

Table 3. Synthesis
EDA Vendor Product Name Design Solution

Mentor Graphics

Precision RTL

Logic synthesis

Precision RTL Plus

Advanced logic synthesis

Precision Physical

Timing closure tool

Synopsys

Synplify Pro

Logic synthesis tool

Synplify Premier

Timing closure tool

Back to Top

Table 4. Simulation
EDA Vendor Product Name Design Solution

Aldec, Inc.

Aldec Active-HDL

Simulation

Aldec Riviera-PRO

Simulation

Cadence Design Systems,Inc.

Incisive Enterprise Simulator

Simulation

Mentor Graphics

ModelSim

Simulation

Questa

Simulation

Simucad Design Automation

SILOS

Simulation

Symphony EDA

VHDL Simili

Simulation

SynaptiCAD

VeriLogger

Simulation

Synopsys

VCS

Simulation

Back to Top

Table 5. Verification
EDA Vendor Product Name Design Solution

Aldec, Inc.

ALINT

RTL checker

Blue Pearl

Indigo RTL Analysis

RTL checker

Cobalt Timing Constraints Generation

Constraints generator

Azure Constraints Validation

Constraints validation

Cadence Design Systems,Inc.

Encounter Conformal Equivalence Checker

Formal verification

DAFCA

ClearBlue FPGA

In-system verification

EMA Design Automation

TimingDesigner

Timing verification

FishTail

Focus

Constraints generator

Confirm

Timing-exception verification

ReConfirm

Timing-exception validation

GateRocket

RocketDrive

Functional verification

RocketVision

Functional verification

Mentor Graphics

Formal Pro

Equivalence checking

0-In Formal Verification

Functional verification

0-In CDC

Clock domain crossing verification

Real Intent

Meridian

Clock domain crossing verification

SynaptiCAD

TestBencher Pro

Testbench generator

WaveFormer Pro

Timing verification

Synopsys

LEDA

RTL checker

Identify and Indentify Pro

Integrated RTL debug

Magellan

Functional verification

Formality

Formal verification

Temento Systems

Dialite – Platform Edition

In-system verification and integrated RTL debug

AMBA Bus Trace Analyzer

In-system verification

TransEDA

VN-Spec

Specification checker

VN-Check

RTL checker

VN-Cover

FSM coverage tool

Coverability Analysis

Code coverage tool for simulation and testbench generation

Assertain-HDL

RTL checker for simulation coverage

Assertain-ABV

RTL checker for functional verification coverage

Back to Top

Table 6. Board-Level Design
EDA Vendor Product Name Design Solution

Agilent Technologies

Advanced Design System (ADS)

Signal integrity analysis

Altium

Altium Designer

PCB board schematics and layout
Signal integrity analysis

Cadence Design Systems,Inc.

Allegro FPGA System Planner

FPGA I/O planning

OrCAD FPGA System Planner

FPGA I/O planning

Allegro PCB SI

Signal integrity analysis

OrCAD Signal Explorer

Signal integrity analysis

Allegro Design Entry HDL
Allegro Design Entry CIS

PCB board schematics

Cadence OrCAD Capture and Capture CIS

PCB board schematics

Allegro PCB Design

PCB board layout

OrCAD PCB Designer

PCB board layout

Mentor Graphics

I/O Designer

FPGA I/O planning

HyperLynx SI

Signal integrity analysis

DxDesigner

PCB board schematics

PADS

PCB board schematics and layout

Expedition Enterprise

PCB board layout

Board Station

PCB board layout

Signal Integrity Software, Inc. (SiSoft)

Quantum-SI

Signal integrity analysis

Synopsys

HSPICE

Signal integrity analysis

Taray, Inc

7Circuits

FPGA I/O planning

Zuken

CR-5000

PCB board schematics and layout

Back to Top

Table 7. ASIC Prototyping
EDA Vendor Product Name Design Solution

Auspy Development Inc.

Auspy Partition System II

Multi-chip partitioning system

Synopsys

Certify

Multi-chip partitioning system

Back to Top

Related links

  • Embedded software partners
  • Altera IP and development kit partners
  • Altera design services partners
  • SPICE models for Altera devices
  • ASIC Prototyping in Stratix® FPGAs
Rate This Page


  • Logic Design
    • Quartus II Subscription Edition
      • Design Entry & Synthesis
      • Verification & Board Level
      • Optimization
    • Quartus II Web Edition
    • ModelSim-Altera
    • What's New
  • DSP Design
    • DSP Builder
  • Getting Started
    • FPGAs & CPLDs
    • HardCopy ASIC
  • Switching to Quartus II
    • ASIC Users
    • Xilinx ISE Users
    • MAX+PLUS II Users
  • Partners
    • EDA Partners
  • Ordering & Downloading
    • Ordering
    • Downloading
    • Licensing
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates