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The Altera® Commitment to Cooperative Engineering Solutions (ACCESS) program ensures that you have a complete design solution in designing, verifying, and integrating Altera FPGAs and HardCopy® ASICs into your systems. |
List of ACCESS Program Partner Solutions by:
- System-level design
- Design creation
- Synthesis
- Simulation
- Verification
- Board-level design
- ASIC prototyping
| ACCESS Program Partner | System- Level Design | Design Creation | Synthesis | Simulation | Verification | Board-Level Design | ASIC Prototyping |
| Aldec, Inc. |
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| Agilent Technologies |
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| Agnisys Technology Pvt Ltd | |
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| Altium |
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| Auspy Development Inc. |
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| Blue Pearl |
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| Bluespec |
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| Cadence Design Systems,Inc. |
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| Duolog Technologies |
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| EMA Design Automation |
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| FishTail |
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| Impulse Accelerated Technologies |
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| Mentor Graphics |  |
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| NEC |
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| PDTi | |
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| Poseidon Design Systems | |
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| Real Intent |
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| Sigasi |
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| Signal Integrity Software, Inc. (SiSoft) | |
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| Synopsys® | |
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| Zuken | |
| Table 1. System-Level Design | ||
| EDA Vendor | Product Name | Design Solution |
| Altium | Altium Designer | High-level design tool |
| Agnisys Technology Pvt Ltd | IDesignSpec | Register map management |
| Bluespec | Bluespec Compiler | High-level synthesis |
| Cadence Design Systems,Inc. | C-to-Silicon Compiler | High-level synthesis |
| Duolog Technologies | Socrates | Register map management |
| Impulse Accelerated Technologies | ImpulseC CoDeveloper | High-level synthesis and simulation |
| NEC | CyberWorkBench | High-level synthesis |
| PDTi | SpectaReg | Register map management |
| Poseidon Design Systems | Triton Tuner | System-level simulation |
| Triton Builder | High-level synthesis | |
| SynaptiCAD | TestBencher Pro | High-level design tool |
| Synopsys | Synphony Model Compiler | High-level synthesis solution |
| Table 2. Design Creation | ||
| EDA Vendor | Product Name | Design Solution |
| Mentor Graphics® | HDL Designer | Project management, design entry, and analysis tool |
| Sigasi | Sigasi HDT | Design entry, code comprehension, project management, and collaboration |
| Table 3. Synthesis | ||
| EDA Vendor | Product Name | Design Solution |
Logic synthesis |
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Advanced logic synthesis |
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Timing closure tool |
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Logic synthesis tool |
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Timing closure tool |
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| Table 4. Simulation | ||
| EDA Vendor | Product Name | Design Solution |
Simulation |
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Simulation |
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| Cadence Design Systems,Inc. | Simulation |
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Simulation |
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Simulation |
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| Symphony EDA | VHDL Simili | Simulation |
| SynaptiCAD | VeriLogger Extreme | Simulation |
| Synopsys | Simulation |
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| Table 5. Verification | ||
| EDA Vendor | Product Name | Design Solution |
| Aldec, Inc. | ALINT | Register transfer level (RTL) checker |
| Analyze RTL | RTL checker |
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| Create Timing Constraints | Constraints generator |
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| Cadence Design Systems,Inc. | Encounter Conformal Equivalence Checker | Formal verification |
| EMA Design Automation | TimingDesigner | Timing verification |
| Focus | Constraints generator |
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| Confirm | Timing-exception verification |
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| ReConfirm | Timing-exception validation |
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| FormalPro | Equivalence checking |
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| Questa Formal Verification | Functional verification |
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| Questa Clock-Domain Crossing Verification | Clock domain crossing verification |
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| Real Intent | Meridian CDC | Clock domain crossing verification |
| TestBencher Pro | Testbench generator |
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| WaveFormer Pro | Timing verification |
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RTL checker |
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Functional verification |
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Formal verification |
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| ProtoLink Probe Visualizer | Integrated RTL debug for FPGA prototype board |
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| Dialite – Platform Edition | In-system verification and integrated RTL debug |
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| AMBA Bus Verification | In-system verification |
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Specification checker |
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RTL checker |
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Finite state machine (FSM) coverage tool |
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Code coverage tool for simulation and testbench generation |
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RTL checker for simulation coverage |
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RTL checker for functional verification coverage |
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| Table 6. Board-Level Design | ||
| EDA Vendor | Product Name | Design Solution |
| Agilent Technologies | Advanced Design System (ADS) | Signal integrity (SI) analysis |
| Altium | Altium Designer | PCB board schematics and layout |
| Allegro FPGA System Planner | FPGA I/O planning |
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| OrCAD FPGA System Planner | FPGA I/O planning |
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| Allegro PCB SI | SI analysis |
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| OrCAD Signal Explorer | SI analysis |
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| Allegro Design Authoring Allegro Design Entry Capture / Capture CIS |
PCB board schematics |
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| Cadence OrCAD Capture and Capture CIS | PCB board schematics |
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| Allegro PCB Designer | PCB board layout |
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| OrCAD PCB Designer | PCB board layout |
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| I/O Designer | FPGA I/O planning |
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| HyperLynx Signal Integrity (SI) | SI analysis |
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| DxDesigner | PCB board schematics |
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| PADS | PCB board schematics and layout |
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| Expedition Enterprise | PCB board layout |
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| Board Station | PCB board layout |
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Signal Integrity Software, Inc. (SiSoft) |
Quantum-SI | SI analysis |
| Synopsys | HSPICE | SI analysis |
| CR-5000 | PCB board schematics and layout |
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| Table 7. ASIC Prototyping | ||
| EDA Vendor | Product Name | Design Solution |
| Auspy Development Inc. | Auspy Partition System II | Multi-chip partitioning system |
| Synopsys | Certify | Multi-chip partitioning system |
