EDA ACCESS Partner Profiles: Symphony EDA
Overview
Symphony EDA, a leader in HDL simulation technology, is committed to delivering verification solutions with the highest levels of performance, usability, accessibility, and value to the FPGA and CPLD designer.
Symphony EDA’s VHDL SimiliTM is a high-performance VHDL compiler and simulator wrapped in a powerful, integrated development environment, ideal for register transfer level (RTL) and gate-level simulation of programmable logic designs ranging from thousands to several millions of gates. Available for Windows or Linux platforms, VHDL Simili includes a comprehensive waveform interface (SonataTM), language-sensitive design editor, smart compilation and project management, tool command language (Tcl)-based command console, batch mode capability (for regressions or TEXTIO redirection), and full language/extended library support (including VITAL and SDF). VHDL Simili is available in Standard-Edition or Professional-Edition. The Professional-Edition incorporates additional productivity features such as global performance optimizations, VITAL Level-0 and Level-1 acceleration, advanced source-level debugging (breakpoints, signal force/release), and fast code coverage with statistical and graphical reporting. VHDL Simili is shipped with Quartus® II library compilation scripts to enable simulation of all families of high-performance FPGAs, low-cost FPGAs, transceiver FPGAs, CPLDs, and structured ASICs from Altera.
VHDL Simili is based on Symphony EDA’s second generation ZEOS (Zero-Overhead-Stack)TM technology, which enables fast, on-the-fly language interpretation and simulation kernel execution in a compact memory footprint. For more information on Symphony EDA’s simulation technology, go to www.symphonyeda.com.
Tools
Table 1 lists design tools supporting Altera devices.
| Table 1. Design Tools Supporting Altera Devices |
| Design Flow |
Tool Name |
Comments |
| Design Entry |
|
Design Entry & Rule Check
|
VHDL Simili |
VHDL Simili features an IEEE 1076-93 VHDL language compliant compiler with built-in standard libraries, and also supports VHDL’87 style FILE declarations, IEEE 1164 (std_logic) libraries, Synopsys libraries (std_logic_arith, std_logic_signed, std_logic_unsigned, etc.), VITAL 95/2000 (IEEE 1076.4) packages, and SDF 2.1, 3.0, and 4.0 for back annotation of timing data. All packages have accelerated versions which can be selectively disabled at run-time. VHDL Simili provides a user-configurable, language-sensitive text editor as well as automatic file ordering and smart compilation for complex design hierarchies.
|
| Verification |
|
Simulation & Timing Analysis
|
VHDL Simili |
Based on Symphony EDA’s proprietary ZEOS technology, VHDL Simili delivers high-performance simulation of RTL and gate-level netlists. The Sonata graphical interface includes a powerful tool command language (Tcl)-based console for simulation control and a fast, feature-rich waveform viewer. VHDL Simili Professional-Edition additionally allows breakpoint setting, signal force/release, stop/continue from ASSERT/REPORT statements, and efficient code coverage with HTML/text/graphical reporting.
|
Contact Information
For additional technical or sales information, contact Symphony EDA at:
Symphony EDA
10844 SW Nutcracker Ct.
Beaverton, OR 97007
Sales Inquiries:
Tel: (408) 333-9199
Fax: (408) 834-4817
Email: sales@symphonyeda.com
Technical Support:
Tel: (503) 430-8410
Fax: (503) 430-8405
Email: support@symphonyeda.com
URL: http://www.symphonyeda.com
|
Literature
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