EDA ACCESS Partner Profiles: Synopsys, Inc.
Overview
Synopsys’ full suite of best-in-class tools enables designers to create and verify complex FPGA and system-on-chip (SoC) designs from concept to silicon. Synopsys provides system-level to silicon-level verification, a complete front-to-back design and test environment, design reuse technology, and professional services to help its customers get their silicon working quickly and accurately. Synopsys’ products improve its customers’ designs in virtually every metric, including performance, complexity, silicon area, cost, power consumption and time-to-market.
Synopsys has a long-standing relationship with Altera that has resulted in the availability of high-powered, leading-edge tools in Altera’s design software environment. Synopsys and Altera have worked together to tune Design Compiler FPGA to the Stratix® and CycloneTM device series, allowing you to achieve high-quality FPGA results from your ASIC environment. The companies have also worked together to provide a complete front-to-back solution for Altera’s HardCopy® and HardCopy II structured ASIC device families. Synopsys Professional Services, a qualified Altera Consultant Alliance Program (ACAPSM) member, provides an experienced set of designers around the world who are well versed in designing with Altera devices. Altera provides numerous libraries that have been qualified with Synopsys products and is a member of Synopsys’ Semiconductor Vendor Program.
Synopsys implementation and verification flows allow techniques commonly used in ASIC design to be applied to today’s complex programmable logic devices, making conversions between ASICs and FPGAs straightforward. Broad support for system-level designs involving standard languages like SystemC and SystemVerilog facilitate the direct design of complex SoC devices.
Tools
Table 1 lists design tools supporting Altera devices.
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Table 1. Design Tools Supporting Altera Devices
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Design Flow
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Tool Name
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Comments
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System Level
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Hardware/Software Partitioning & Co-Simulation
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System Studio
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System Studio is an ideal system-level verification tool for multiprocessor systems. It simulates algorithms and architectures and addresses system aspects such as hardware and software tradeoffs, transactional analysis of the architecture, and end-to-end algorithm performance analysis using C/SystemC™. System Studio is tightly integrated with VCS™ to enable smart verification of the RTL implementation.
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Saber
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Saber® is the de-facto standard for mixed-signal, multi-technology simulation, with more than a decade experience and thousands of generic and characterized models in the library (using MAST modeling language). Saber technology allows you to develop and optimize electrical, electronic, mechanical, hydraulic, etc. designs for manufacturing to make designs robust, and to generate documentation and manufacturing data.
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High-Level Design Tools
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DesignWare SystemC Library
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The DesignWare® SystemC Library makes popular off-the-shelf processors and bus models available to the System Studio customer base.
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Design Entry
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Design Entry & Rule Check
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Leda
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Synopsys' Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex designs. Leda’s pre-packaged rules greatly enhance a designer's ability to check HDL code for efficient synthesis, simulation, testability, and reusability.
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Synthesis
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Synthesis
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Design Compiler FPGA
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Design Compiler® FPGA offers architecture-specific synthesis for Stratix and Cyclone FPGAs with ASIC flow compatibility. Advanced algorithms, such as register retiming, optimize the logic for Altera devices resulting in better QoR for complex FPGAs. Because it is integrated into the Design Compiler environment, DC FPGA is unique in offering a fully ASIC compatible flow to ease migration and ASIC prototyping.
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Design Compiler
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Design Compiler® is the synthesis tool used on almost every ASIC and COT design in the electronics industry. It is proven through tens of thousands of successful tape-outs and supported by virtually all silicon and library vendors.
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Module Compiler
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Module Compiler™ is a next-generation module compilation tool that enables designers to reuse their datapath structures to obtain the best implementation for their designs.
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DFT Compiler
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DFT Compiler™ is Synopsys’ next-generation 1-pass design-for-test (DFT) synthesis solution. It delivers DFT transparently within Synopsys’ synthesis flow for seamless optimization of area, power, and timing constraints, and predictable timing closure for fastest time to results.
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Power Compiler
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Power Compiler™ is a leading synthesis tool for simultaneously optimizing the timing, power and area in a chip design. Power Compiler automatically minimizes power consumption and enables pre-synthesis power estimation for budget analysis and architectural explorations that result in lower power and a shorter design cycle.
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Verification
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Simulation
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VCS
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VCS® has evolved from an HDL simulator into a complete RTL verification solution. VCS provides advanced, built-in technologies, including full-featured testbench, complete assertion support, a library of over 50 assertion checkers and comprehensive coverage and analysis, to enable smart verification of complex system-on-chip designs. VCS delivers easy-to-use and easy-to-deploy multi-language simulation for Verilog, VHDL, SystemVerilog and SystemC™.
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VCS MX
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The VCS MX mixed-language verification product delivers the highest performance for designs containing Verilog and VHDL blocks. This product specifically addresses the performance requirements of complex design verification, utilizing customized compiler optimization techniques for Verilog and VHDL. All the built-in technologies, such as full-featured testbench, complete assertions and comprehensive coverage, are also available for mixed-HDL designs.
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Timing Analysis
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PrimeTime
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PrimeTime® is a full-chip, gate-level static timing analyzer targeting complex 100 million-gate designs. It is ideal for large, multi-frequency designs that combine synthesized logic, embedded memories, and microprocessor cores.
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Formal Verification
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Formality
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Formality® is the equivalence checking solution. It uses formal verification techniques to determine if two versions of a design are functionally equivalent. It achieves 100% coverage without the need to create test vectors.
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In-System Debugging
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VERA
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VERA® is a comprehensive testbench automation tool for module, block, and full system verification. It is based on OpenVera™, an open source hardware verification language, developed specifically to meet the unique requirements of functional verification.
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Board Level
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Board Verification
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HSPICE
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HSPICE® offers a high-accuracy circuit simulation environment that combines the most accurate and validated IC device models with advanced simulation and analysis algorithms.
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Other Information
Synopsys Professional Services is a member of ACAP.
Contact Information
For additional information, contact Synopsys at:
Synopsys, Inc.
700 East Middlefield Road
Mountain View, CA 94043 USA
Tel: (650) 584-5000 or (800) 541-7737
E-mail: http://www.synopsys.com/contactus.html
URL: www.synopsys.com
Saber, DesignWare, Leda, Design Compiler, PrimeTime, Formality, VCS, VERA and HSPICE are all registered trademarks of Synopsys, Inc.
Module Compiler, DFT Compiler, Power Compiler, and OpenVera are all trademarks of Synopsys, Inc.
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Literature
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