Quartus II Software Design Features
The Quartus® II design software delivers the highest productivity and performance for FPGAs, CPLDs, and structured ASICs and offers numerous design features to accelerate the design process:
- Incremental compilation to reduce the design cycle time
- SOPC Builder for system-level design
- MegaWizard® Plug-In Manager to quickly and easily integrate a broad portfolio of intellectual property (IP) cores
- Power analysis tools to meet stringent power requirements
- A memory compiler function to easily use embedded memory
The Quartus II software enables you to create and deliver FPGA, CPLD, and structured ASIC designs with unmatched levels of performance and faster time-to-market.
The Quartus II software supports VHDL and Verilog HDL design entry, graphical-based design entry methods, and integrated system-level design tools. The Quartus II software integrates design, synthesis, place-and-route, and verification into a seamless environment, including interfaces to third-party EDA tools.
Use Incremental Compilation to Improve Productivity
The Quartus II incremental compilation feature enables the most productive incremental design methodology for high-density FPGAs. An industry first, this easy-to-use feature reduces design compilation times up to 70 percent and improves timing closure by allowing you to target design optimization options to individual design partitions and preserve performance in other partitions by leaving them untouched.
Integrate IP Faster
 Altera® software subscriptions include the MegaCore® IP Library and Nios® II Embedded Processor, Evaluation Edition including OpenCore® Plus versions of all Altera off-the-shelf MegaCore functions. Only the Quartus II software features the OpenCore Plus infrastructure technology, allowing you to evaluate the IP in hardware and in simulation before purchasing a license.
The SOPC Builder tool is included with the Quartus II design software. SOPC Builder is an exclusive Quartus II software tool that enables you to rapidly and easily build and evaluate embedded systems. SOPC Builder:
- Integrates off-the-shelf IP from Altera or Altera Megafunction Partner Program (AMPPSM) partners
- Enables you to create your own reusable custom components to include in your systems
- Generates HDL to build an interconnect fabric optimized for the requirements of each system
- Outputs system testbench suites
- Outputs a custom software development kit (SDK) based on the memory map and components of the generated system
SOPC Builder allows you to focus on custom user logic design to differentiate your system by eliminating manual system integration tasks. All versions of the Altera Quartus II design software include the SOPC Builder system generation tool.
You can use Altera’s MegaWizard Plug-In Manager to parameterize and instantiate IP functions easily, reducing design entry time and improving design performance. You can use the MegaWizard Plug-In Manager with the library of parameterized modules (LPM) functions included with the Quartus II software as well as Altera or AMPP partner IP megafunctions.
Assign and Validate I/O Pins Early in the Design Cycle
The Quartus II software can perform up-front I/O assignment and validation (PDF) so PCB layout can begin earlier in the design process. You can now change and validate pin assignments at any time without performing a design compilation. The new Quartus II pin planner feature makes it easy to make and manage pin assignments.
Analyze and Optimize Power
The Quartus II software PowerPlay power analysis and optimization technology is designed to enable you to accurately analyze and optimize both dynamic and static power consumption. The PowerPlay tools produce detailed reports that you can use to optimize thermal power dissipation on a block-type or design-hierarchy basis.
Memory Compiler
The Quartus II memory compiler function helps you use embedded memory in Altera FPGAs. Quartus II software can dynamically generate waveforms for FIFO buffers and RAM read operations based on current configuration selections. More information on inferring memory in VHDL or Verilog HDL code is available in the Design & Synthesis (PDF) section of the Quartus II Handbook.
CPLD, FPGA, and HardCopy Structured ASIC Support
In addition to CPLDs and FPGAs, the Quartus II software now features support for the HardCopy® series structured ASICs using the same design tools, IP, and verification methodologies used for FPGA design. For the first time in the industry, you can design for a structured ASIC with predictable design performance and power consumption, using easy-to-use FPGA design software.
Automate Design Flows Using Command-Line and Scripting Feature Sets
You can run the Quartus II software synthesis, place-and-route, timing analysis, and programming modules independently from the command line or from the Quartus II software GUI. In addition to Synopsys design constraint (SDC) scripting support, the Quartus II software includes an easy-to-use tool command language (Tcl) interface to support custom design flow creation and to satisfy the needs of power users. More information is available in the Scripting & Constraint Entry (PDF) section of the Quartus II Handbook.
Learn About Quartus II Features With Advanced Tutorials
The Quartus II software includes a walk-through tutorial for creating a project and performing common design, synthesis, place-and-route, and verification tasks. The Quartus II software also includes tutorials explaining how to convert MAX+PLUS® II software projects into Quartus II software projects and advanced tutorials to help you quickly master designing with the latest devices and methodologies.
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