Quartus II Incremental Compilation
#1 in Performance and Productivity for High-Density FPGA Design
Quartus® II software includes the FPGA industry’s first incremental compilation feature. This feature supports both top-down and bottom-up, team-based design and delivers faster compilation times for design iterations while preserving performance, enabling Quartus II software to be the productivity leader for high-density FPGA design. Using Quartus II software for your high-density FPGA designs now gives you the fastest path to design completion.
Performance of Design Blocks Maintained Throughout System Integration
The Quartus II incremental design capability was enhanced to include a team-based project management flow which provides significant productivity advantages for team-based design. System architects can first define a project using a top-down approach. With the new Project Manager Interface (see Figure 1), you can generate all the bottom-up design partition projects enabling individual engineers to independently develop and optimize functions which can then be easily integrated into a complete design. System architects can incrementally integrate optimized design blocks as they are ready, while the performance of the design blocks is maintained throughout system integration.
Figure 1. Project Manager GUI
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Perform More Iterations Each Day to Maximize Productivity
By reducing compilation times (see Figure 2), you can now jump from only one to two design iterations per day to as many as four to ten iterations per day, dramatically improving your productivity.
Figure 2. Reduce Compilation Times and Perform More Iterations for High-Density FPGA Designs
Reach Timing Closure Faster
Incremental compilation enables you to identify physical and logical partitions for synthesis and fitting/logic placement, as shown in Figure 3.
Figure 3. Design Partitions for Incremental Compilation
The Quartus II software preserves your assigned partitions when processing your design, allowing you to optimize specific partitions while keeping others intact. Advanced optimization techniques can cause compilation times to increase, but the incremental compilation feature enables you to limit this effect and see timing closure improvements. Simply use advanced optimization techniques such as physical synthesis on specific design partitions while leaving other partitions untouched.
For example, if Partition Top and Partition F (see Figure 3) are already meeting performance requirements, you can now optimize overall design performance further by making changes only to Partition B or by recompiling the design with physical synthesis turned on.
Ease of Use
Partitions can easily be assigned from the hierarchy view in the Quartus II software project navigator, as shown in Figure 4.
Figure 4. Identifying Design Partitions in the User Interface
After identifying how a design is partitioned, you can gain a high degree of control over how designs are processed by simply setting a netlist type property for each partition. Table 1 shows the available settings.
| Table 1. Partition Netlist Types |
| Netlist Type |
Behavior |
| Source |
Compile partition using the associated design source file or files. |
| Post-Synthesis |
Compile partition using the previous synthesis results, if available, so source file changes are detected. |
| Post-Fit |
Compile partition using the previous placement/fitting results, if available, and if no source file changes are detected. |
| Post-Fit [Strict] |
Preserves post-fit results if a post-fit netlist is available. This setting differs from the Post-Fit setting in that it causes the compiler to ignore any design changes associated with the partition. |
| Empty |
Do not compile partition, just connect ports from other partitions to the ports of this partition. This feature is useful for block-based design when some partition designs are not yet complete. |
Scripting Support
If you prefer script-based design flows, you can easily set up designs to use the incremental compilation feature, as shown below:
set project top_project
package require :: quartus::flow
project_open $project
# Turn on Incremental Compilation
set_global_assignment –name INCREMENTAL_COMPILATION \
FULL_INCREMENTAL_COMPILATION
# Set up the partitions
set_instance_assignment –name PARTITION_HIERARCHY \
db/A_inst –to A –section_id “Partition_A”
set_instance_assignment –name PARTITION_HIERARCHY \
db/B_inst –to B –section_id “Partition_B”
# Set the netlist type to post-fit for subsequent
# compilations so previous results are used if no design
# changes are detected
set_global_assignment –name PARTITION_NETLIST_TYPE \
POST_FIT –section_id “Partition_A”
set_global_assignment –name PARTITION_NETLIST_TYPE \
POST_FIT –section_id “Partition_B”
# Run initial compilation
execute_flow –full_compile
project_close
Find out more about Quartus II software tool command language (Tcl) scripting support.
Third-Party Synthesis Support
You can use all third-party synthesis tools with the Quartus II incremental compilation feature, including:
- Synplicity Synplify tools
- Mentor Graphics® Precision and LeonardoSpectrum™ tools
- Synopsys DC FPGA
For more details on using these tools with the Quartus II software incremental compilation feature, refer to the Quartus II Handbook.
Device Support
The Quartus II incremental compilation feature is available in the Quartus II Subscription Edition version 6.1 for the following families:
- Stratix® III FPGAs
- Stratix II FPGAs
- Stratix FPGAs
- Stratix GX FPGAs
- Cyclone® II FPGAs
- Cyclone FPGAs
- HardCopy® II Devices
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