Quartus II Software Technology Leadership Delivers Highest FPGA and CPLD Performance
Quartus® II design software's technology leadership delivers the highest available performance for high-density FPGA designs, low-cost FPGA designs, and CPLD designs, as shown in Table 1.
| Table 1. Quartus II Performance Leadership as Compared to Xilinx ISE (1) |
| Device Category |
Devices Compared |
Winner |
Winner Margin |
Low-Cost FPGA
(65 nm) |
Cyclone® III FPGA vs. Spartan-3 |
 |
Three speed grades |
High-Density FPGA
(65 nm) |
Stratix® III FPGA vs. Virtex-5 |
|
13% |
High-Density FPGA
(90 nm) |
Stratix II FPGA vs. Virtex-4 |
|
18% |
High-Density FPGA
(130 nm) |
Stratix FPGA vs. Virtex-II Pro |
Even |
0% |
Low-Cost FPGA
(90 nm) |
Cyclone II FPGA vs. Spartan-3 |
|
Three speed grades |
| CPLD |
MAX® II CPLD vs. CoolRunner-2 |
|
76% |
Note:
- The Programmable Logic Performance Leadership section of the Altera® website includes technical details, timing analysis techniques, and exact benchmarking methods.
Winning Advantage Starts Years in Advance
Traditional programmable logic device (PLD) development techniques optimize silicon hardware architectures and then go back and develop software toolchains to support that architecture. Altera uses Quartus II software modeling tools and unique Altera-developed device modeling tools to experiment with thousands of device and software algorithm parameters. Using this information, Altera concurrently develops optimal silicon architectures and software support.
Only FPGA Vendor-Integrated Physical Synthesis Technology
Quartus II software includes the only integrated physical synthesis optimization technology available from an FPGA vendor. Quartus II physical synthesis options are applied during the fitting stage of the compilation process and can be applied regardless of the synthesis tool used.
Faster Timing Closure
You can take advantage of powerful timing closure flow features to optimize designs beyond push-button results. Quartus II software's timing closure flow is highlighted by the inclusion of integrated physical synthesis tools and a rich set of graphical analysis and editing tools supported by unmatched cross-probing capabilities.
Easiest-to-Use Design Optimization Technology
Quartus II software satisfies timing requirements using a push-button design flow for most designs. When you need to go beyond push-button results, Quartus II software now includes exclusive tools to make design optimization simple:
- Design Space Explorer (PDF) uses automated technology to increase average register-to-register fMAX design performance by 21 percent.
- Timing optimization advisor tool provides a virtual field application engineer inside Quartus II software. This tool provides specific advice on optimizing design timing performance based on the current design project settings and assignments.
Maintain Performance When Implementing Late-Stage Design Changes
A traditional problem with programmable logic design software has been maintaining performance as later design changes are introduced. However, Quartus II software makes it easy to implement late-stage design changes. New fine-grained incremental design editing and compilation technologies provide the best support for post place-and-route design changes. These technologies include:
- Quartus II Chip Planner (Floorplan & Chip Editor)
- Ability to lock down placement and routing in LogicLock™ regions
- Using incremental compile to make changes to only a portion of the design that changed
Only Parallel Development for FPGAs and Structured ASICs
Only Quartus II software provides seamless migration between FPGA design and structured ASIC design. By enabling compilation for HardCopy® series structured ASIC devices, Quartus II software provides the only risk-free path to higher performance and lower device costs.
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