Place-and-Route
Quartus® II design software delivers the highest performance available for high-density FPGA designs through its place-and-route technology leadership. Quartus II software establishes technology and productivity leadership with the only physical-synthesis optimization technology available from an FPGA vendor and the industry's first comprehensive incremental compilation feature for high-density FPGA design. Only Quartus II software place-and-route technology supports FPGAs, CPLDs, and structured ASICs in a single easy-to-use environment.
Altera continually refines Quartus II software place-and-route features based on high-level design optimization research and direct feedback from thousands of customers worldwide.
Faster Timing Closure
Quartus II software place-and-route algorithms can use register packing, register retiming, automatic logic duplication, and what-you-see-is-what-you-get (WYSIWYG) primitive re-synthesis technologies to pack more logic than ever into a given device and deliver superior fMAX performance even at extremely high logic utilization. You can use powerful timing closure flow features to optimize designs beyond push-button results. The Quartus II software timing closure flow includes features such as:
Timing and Resource Optimization Advisors
Quartus II software includes timing and resource optimization advisor tools to provide specific advice on optimizing design timing performance and resource utilization based on the current design project settings and assignments. Figure 1 shows an example of the Timing Optimization Advisor interface.
Figure 1. Timing Optimization Advisor
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Improved Productivity With Incremental Compilation
The Quartus II incremental compilation feature enables the most productive incremental design methodology for high-density FPGAs. An industry first, this easy-to-use feature reduces design compilation times up to 70 percent and improves timing closure by allowing you to target design optimization options to individual design partitions and preserve performance in other partitions by leaving them untouched.
Compile Times Minimized
The Quartus II software now supports parallel processing during compilation for computers with multiple processors, which can reduce compile times by up to 15 percent. The Quartus II software includes fitter effort settings that you can select based upon your design needs, allowing you to control compile times. Figure 2 shows the available fitter effort settings. Auto Fit is the default setting for a new project. When a design’s timing requirements are easily satisfied, the Auto Fit feature provides an average of 40 percent compile time reduction. Enter your desired minimum target slack to force the software to gain some margin on your timing constraints before reducing optimization effort. Selecting the Fast Fit option provides an average of 50 percent faster compilation times with an average of 5 to 10 percent lower design performance.
Figure 2. Quartus II Fitter Effort Levels
Late-Arriving, Post-Place-and-Route Design Changes Easily Supported
It is now quick and painless for you to implement late-arriving design changes. Quartus II software's new fine-grained incremental design editing and compilation technologies give you the best support for post-place-and-route design changes. These technologies include:
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