Timing Closure Methodology Features
Following are some of the major advantages of the Quartus® II software timing closure:
Improve Timing Closure Using the LogicLock Block-Based Design Flow
 A design's timing closure is most successful if the design also has an explicit hierarchy. Quartus II users can leverage the LogicLock block-based design flow to further improve inter-block and intra-block timing results. Designers can lock routing as well as placement when using the LogicLock design.
More information is available on the LogicLock block-based design page.
Save Engineering Time with Advanced Place-and-Route and Physical Synthesis Algorithms
Quartus II design software includes the most technologically advanced place-and-route algorithms available to optimize the performance and area of a device's design. Netlist optimizations are push-button features that offer improvements to fMAX results by making modifications to the netlist.
Different optimization types will produce varying results depending on the characteristics of the design. Quartus II software can perform what-you-see-is-what-you-get (WYSIWYG) primitive re-synthesis to optimize netlists from third-party synthesis tools to use all available device resources. Physical synthesis register retiming will move registers and logic to balance delays between registers.
When logic delay was the primary source of design performance bottlenecks, designers often optimized their designs by reducing the design’s logic amount. Today, because routing is the primary source of delay, duplicating registered logic can increase the design’s performance significantly. Quartus II software can perform physical synthesis optimizations to automatically duplicate logic resources as needed to improve performance or I/O timing.
Increase Performance Further with the New Design Space Explorer Script
The Quartus II software design space explorer script increases average design performance by 20 percent—automatically applying combinations of netlist optimizations and advanced Quartus II software compiler settings. Optimum settings are reported back to you, so you can gain faster performance and run times for subsequent compilations.
Increase Performance Using the Automatic Logic Duplication Feature
When logic delay was the primary source of design performance bottlenecks, designers often optimized their designs by reducing the design's logic amount. Today, because routing is the primary source of delay, duplicating registered logic can increase the design's performance significantly. Altera has incorporated this automatic logic duplication feature to duplicate registered logic, resulting in increased performance.
The new Quartus II software RTL viewer feature provides a schematic representation of VHDL and Verilog designs that can be used to analyze a design’s structure before further behavioral simulation, synthesis, and place-and-route steps are performed. Technology map viewer provides a schematic representation of how designs are implemented in a device architecture after synthesis and place and route and may include timing information to aid in debugging and optimization.
Save Engineering Time Using the Timing Optimization Advisor
Quartus II software version 4.1 and later includes timing and resource optimization advisor tools to provide specific advice on optimizing design timing performance and resource utilization based on the current design project settings and assignments. There are detailed instructions and links to software features to implement the proposed suggestions. Figure 1 shows an example of the timing optimization advisor interface.
Figure 1. Timing Optimization Advisor
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The timing wizard, shown in Figure 2, is a user interface that walks new Quartus II software user through the steps of making timing assignments in the Quartus II user interface.
Figure 2. Timing Wizard View
Support ASIC Timing Constraints
Quartus II software, version 2.1 and later, supports the commonly used Synopsys design constraint (SDC) format. This format allows timing constraints to be defined once in a single script that can be utilized by all tools in the flow. You can also reuse your existing ASIC timing constraint files in SDC format to migrate your designs to an Altera® FPGA.
Improve Accuracy of Third-Party Synthesis Software Performance Estimates
Most of Altera's intellectual property (IP) is treated as "black boxes" by the third-party synthesis tools. The clear box model is a synthesizable model in VHDL or Verilog HDL that allows third-party synthesis tools to optimize at the IP boundary and to provide more accurate timing estimates.
Cross Probe Between Quartus II Software and Third-Party Synthesis Software
Cross probing provides better linkages and interaction between third-party synthesis tools and post-place-and-route results. Using the .xrf file, you can link from the Quartus II timing analyzer and floorplan directly into the pre-synthesis source code via the Synplify/Synplify Pro user interface. The cross probing feature is useful to illuminate which Verilog HDL code can be modified to further improve performance.
Close Timing Faster Using the Timing Closure Floorplan Editor
The timing closure floorplan editor gives you the ability to see fitter-created assignments and user-created assignments simultaneously. Furthermore, it contains multiple views of timing-related data, including:
- Physical timing estimates and interactive delay calculation
- LogicLock region connectivity
- LogicLock region timing
- Critical path display options
- Routing congestion view to help guide placement of LogicLock regions for optimal performance
As shown in Figure 3, the timing closure interactive floorplan shows delay estimates between locations on the device. It also shows the connectivity, or number of paths, between LogicLock regions (Figure 4).
Figure 3. Delay Estimates
Figure 4. Connectivity Between LogicLock Regions
Use Path-Based Assignments to Improve Performance on Critical Timing Paths
The path-based assignments feature allows you to make placement assignments directly to a failing path from within the timing analysis tool in the Quartus II software. To use the feature, simply right-click on a failing path and select the menu item to assign the path to a LogicLock region. As shown in Figure 5, the path-based assignments window also supports wildcard searches when automatically assigning a path to a LogicLock region.
Figure 5. Path-Based Assignments Window
Implement Post-Place-and-Route Design Changes Easily Using the Chip Planner
The chip planner feature enables designers to view the internal structure of Altera devices and incrementally edit logic element (LE) and I/O cell configuration after place-and-route has already been performed. Quartus II software, version 4.0 and later, also allows you to add or remove terms in an LE's “look-up table sum equation” to create or delete connections between LEs. Changes can be implemented in a device in minutes without re-compiling a design. Changes are restricted to a particular device resource(s), so timing closure is maintained in the remaining portions of the design.
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