Quartus II Software Design Features Questions and Answers
Q. What is the TimeQuest timing analyzer tool?
A. The TimeQuest timing analyzer provides comprehensive native support for the industry-standard SDC timing format. TimeQuest timing analyzer lets you create, manage, and analyze timing constraints and quickly perform advanced timing verification. TimeQuest timing analyzer is available in Quartus® II Subscription Edition software version 6.0 and later and Quartus II Web Edition software version 6.1 and later.
Q. Which Altera® device families does the TimeQuest timing analyzer tool support?
A. TimeQuest timing analyzer supports the following Altera device families: MAX® II CPLDs, Cyclone® series, ArriaTM GX and Stratix® series FPGAs, and HardCopy® II structured ASICs.
Q. Why is Altera using the SDC format in its TimeQuest timing analyzer tool?
A. The SDC timing constraints format provides an accurate, comprehensive, and concise modeling of timing relationships among design signals. SDC is an industry-standard format broadly adopted by ASIC engineers. Through the Synopsys TAP-in Program, Altera developed the TimeQuest timing analyzer's SDC-compliant front-end. Now, FPGA and structured ASIC designers can constrain timing paths more accurately and get a fast, reliable ASIC prototype cycle with tools from Altera and Altera partners.
Q. Can Quartus II software users still use Synopsys PrimeTime to perform timing analysis?
A. Yes. Quartus II software continues to fully support Synopsys PrimeTime.
Q. Will the Quartus II classic timing analyzer and the TimeQuest timing analyzer deliver the same results?
A. Under normal conditions, Quartus II classic timing analyzer and TimeQuest timing analyzer produce consistent timing analysis results. Different results can occur if timing constraints differ, or if you enable advanced features in the TimeQuest timing analyzer (such as rise/fall analysis for HardCopy II structured ASICs and 65-nm FPGA families).
Altera recommends using a timing analysis tool when designing Altera devices. Switching timing engines between compilations causes normal fitter variations, possibly resulting in differing timing results.
Q. Will Altera maintain support for its classic timing analyzer?
A. Yes. Altera recognizes that many Quartus II software users are comfortable with the classic timing analyzer and will continue to support it.
Q. What is the Quartus II software’s incremental compilation technology?
A. Introduced in Quartus II software version 5.0, incremental compilation allows you to divide designs into physical and logical partitions for synthesis and fitting (place-and-route). By using incremental compilation, you can reduce design compile time by up to 70 percent and reach design timing closure more efficiently. This feature supports block-based design, which allows you to preserve the performance of specified blocks while other blocks are undergoing optimization. Incremental compilation also enables top-down and bottom-up design flows, as well as a team-based design methodology.
Q. What are the expanded team-based design features in Quartus II software?
A. Altera's expanded team-based design feature includes a project manager interface for managing device resource and timing budgets. The project manager interface enables the project lead to subdivide the project in a way that eliminates resource conflicts (I/O pins, memory, DSP blocks, etc.) when design blocks are combined at the top level. Designed for use with large or geographically dispersed teams, the new feature allows design teams to more efficiently collaborate in the design of high-density devices. The project manager interface benefits the engineer using a bottom-up design methodology to manage larger and more complex FPGA-based designs. The new feature builds upon the incremental compilation design features introduced in Quartus II software version 5.0.
General Q & A
Q. What is Altera’s Quartus II design software?
A. Altera's Quartus II design software is the industry's first and only design tool to offer a unified design flow for the development of FPGAs, CPLDs, and structured ASICs. Quartus II design software accelerates performance, boosts productivity, and easily addresses potential design delays such as late-arriving, post place-and-route design changes.
Q. How can I learn more about Quartus II software features and supported design flows?
A. Altera provides various avenues for you to receive Quartus II technical information and training:
Q. What is an Altera software subscription?
A. Altera's software subscription program simplifies the process of obtaining Altera design software by consolidating development software products and maintenance charges into one annual fee. The annual subscription for the Altera design software is $2,000 for a node-locked personal computer (Windows PC) license; subscriptions are also available to support other operating systems.
Altera's Quartus II Subscription Edition design software includes the SOPC Builder system generation and integration tool, Mentor Graphics® ModelSim®-Altera software, Altera's IP Base Suite including ten of the most popular intellectual property (IP) cores (DSP, memory controller, and Gigabit Ethernet MAC cores), perpetual licenses for several popular Altera MegaCore® IP functions, the MegaCore IP Library including OpenCore Plus editions of all Altera MegaCore design-ready IP functions, the Nios® II Embedded Design Suite, and 12 months of software upgrades.
Q. What is the difference between Quartus II Web Edition software and the Quartus II Subscription Edition software included in subscription products?
A. Quartus II Web Edition software includes most of the features included in the Quartus II Subscription Edition software and everything customers need to design for Altera's latest CPLD and low-cost FPGA families. Quartus II Web Edition software also includes support for entry-level members of Altera's high-density FPGA families.
Q. Is the Quartus II software included in Altera development kits different from the Quartus II software included in Altera software subscriptions?
A. The Quartus II Development Kit Edition (DKE) software and the Quartus II Subscription Edition software are equivalent in performance and functionality. Several differences exist in licensing and bundled IP. Altera's Quartus II Subscription Edition offers access to upgrades for one year and perpetual software use. The Quartus II Development Kit Edition software includes access to upgrades along with software use for one year only. At the end of the year, customers can upgrade their Development Kit Edition software to the Subscription Edition software at a discounted price, or use the free Web Edition software version. Altera's IP Base Suite, including nine of the most popular IP cores (DSP, memory controller, and Gigabit Ethernet MAC cores), is available only in the Quartus II Subscription Edition software.
Q. Is Mentor Graphics ModelSim-Altera software included with the Quartus II software?
A. There are two versions of the Mentor Graphics ModelSim-Altera software:
- ModelSim-Altera Edition (Use With Quartus II Subscription Edition Software)—ModelSim-Altera Edition software is available with an Altera software subscription purchase and can be licensed for Windows, UNIX, or Linux platforms to support either VHDL or Verilog HDL simulation.
- ModelSim-Altera Web Edition (Use With Quartus II Web Edition Software)—The ModelSim-Altera Web Edition software is available free of charge for use with Quartus II Web Edition and can only be licensed for the Windows platform to support either VHDL or Verilog HDL simulation.
You can find more information on the differences between these software editions on the ModelSim-Altera Software web page.
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