Quartus II Synthesis
Quartus® II software includes a comprehensive integrated synthesis solution and advanced integration with leading third-party synthesis software vendors. Quartus II software, together with Altera’s third-party partners—Mentor Graphics®, Synopsys, and Synplicity—enables you to achieve the highest possible performance from Altera® devices in the shortest time.
Quartus II Integrated Synthesis
Quartus II integrated synthesis (QIS) supports SystemVerilog-2005, Verilog-2001, Verilog-1995, VHDL 1993, and VHDL 1987 standards, and also supports Altera AHDL and schematic (block design file) design entry.
QIS includes advanced synthesis options and compiler directives (attributes) to guide the synthesis process to achieve optimal results. Included in these synthesis options is the PowerPlay power analysis and optimization option and the multiplexer option. The PowerPlay power optimization option controls how aggressive synthesis optimizes the design for power. The multiplexer optimization option takes advantage of Altera FPGA architectural features to reduce device area usage up to 20 percent to fit designs into a smaller device and save cost.
The incremental synthesis feature in Quartus II software gives you more control over design changes and improves synthesis compilation times for incremental changes. To learn more about the Quartus II integrated synthesis feature, refer to the Quartus II Integrated Synthesis (PDF) chapter of the Quartus II Handbook.
Third-Party Synthesis Software
Altera works closely with third-party synthesis partners so that they can deliver timely support for new Altera device families and new Quartus II software features. As a result, you can use advanced Altera device features directly in your HDL code. You can also use advanced Quartus II software methodologies such as LogicLock™ block-based design. For more information on using third-party synthesis software when designing for Altera devices, refer to the Synthesis (PDF) section of the Quartus II Handbook.
Schematic Representation of Designs
The Quartus II RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, or the constraint entry process.
The Quartus II RTL Viewer (shown in Figure 1) provides a schematic register transfer level (RTL) view of designs that you can use to analyze a design’s structure before you perform further behavioral simulation, synthesis, and place-and-route steps. The RTL Viewer allows you to navigate a design’s hierarchy and locate particular items of interest easily to aid in debugging and optimization. Selected items in the RTL Viewer can be directly traced back to source design files.
Figure 1. Quartus II RTL Viewer
The State Machine Viewer presents a view of finite state machines in your design, including a state machine view, state transition table, and state encoding table. You can use the State Machine Viewer for analysis of your design's state machines during debugging and optimization.
You can use the Technology Map Viewer to debug post-map or post-fit designs at a detailed level. This is accomplished by viewing a logical representation of the design implementations mapped into Altera device primitives. Once you perform the fitting and timing analysis steps, you can highlight critical timing paths and timing information in the display and cross-probed back to design source files, the floorplan editor, or the Quartus II Chip Editor for design optimization.
For more information, refer to the Analyzing Designs with Quartus II Netlist Viewers (PDF) chapter of the Quartus II Handbook.
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