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Table 1. Logic Analyzer Interface Features and Benefits
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| Feature |
Benefit |
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Multiple LAI Cores in a Single Device
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Supports multiple clock domains in a single device.
|
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Multiple LAI Cores in Multiple Devices in a Single JTAG Chain
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Allows multiple devices with multiple clock domains to be analyzed
|
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Auto Detection of Devices in JTAG Chain
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Confirms connection to device before attempting to initiate data capture
|
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Auto Detection of Programming Hardware
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Confirms connection to device before attempting to initiate data capture
|
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Route Signals to Unused Pins
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Allows access to internal signals
|
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Ability to Incrementally Add Nodes, Change Signal Selection and Change Trigger Conditions without a Full Recompilation
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Allows you to change which nodes are monitored without a full design recompilation
|
|
Banks can be From 1 to 256 Signals Wide for Each Core
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Enables monitoring of user-specified bus-width transactions
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Each Mux Supports 1 to 256 Banks
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Each core can mux up to 256 individual banks to enable access to more signals than available pins would normally allow
|
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Resource Usage Estimator
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Provides estimate of resources used by LAI core configurations
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Configurable Registered Outputs (Synchronous)
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Allows you to functionally verify your design
|
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Configurable Unregistered Outputs (Asynchronous)
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Allows you to verify timing issues in your design
|
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Two Types of Output Capture Modes
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Allows you to specify either registered (synchronous) or combinatorial (unregistered) outputs. Synchronous mode enables you to specify user-clock to synchronize output
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Two Types of Power Up States
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User-selectable outputs. Either the default bus (bank0) or tri-stated outputs can be chosen.
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Vendor-Independent Application Program Interface (API) for Source-Level Debugging Tools
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Allows third-party software to utilize LAI core resources
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Literature
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