Quartus II Verification Methods
Quartus® II development software and other tools included in Altera® software subscriptions provide a complete flow for creating high-performance system-on-a-programmable-chip (SOPC) designs, including hardware and software components. These verification and simulation methods are available to you as an Altera design software user:
Design rule checking tools contain a set of customized rules that can be applied early in the design process to check whether the design can be synthesized, simulated, and migrated to a particular device technology. Quartus II software versions 2.2 and later contain design rule checking for all supported device families, and include checking for designs targeted for HardCopy® devices. Altera has worked closely with Synopsys to develop customized rule sets for their Leda design rule checking tools to help you optimize designs targeting Altera devices early in the design process.
In addition to generating verification netlists for use in third-party HDL simulators, Quartus II software version 2.1 and later can create HDL testbench templates that can jump-start your testbench development efforts. Quartus II software can also create complete HDL testbenches from Quartus II software simulator waveform files. The Altera SOPC Builder and DSP Builder software tools generate complete system-simulation models and testbenches that you can run with just a few mouse clicks.
Static timing analysis is a method of analyzing, debugging, and validating a design's performance. Timing analysis measures the delay of every path in the design and reports the design's performance. Quartus II software provides advanced timing analysis features such as multi-cycle and multi-clock analysis. Quartus II software also outputs Standard Delay Format Output (.sdo) industry-standard files and STAMP format files for further analysis by third-party, chip-level or board-level timing analysis tools. More information is available in the Timing Analysis section of the Quartus II Handbook.
As SOPC designs continue to get larger, the number of test vectors required to sufficiently verify a design can grow exponentially. Formal verification, a relatively new verification technology that uses mathematical algorithms to verify a post-place-and-route netlist, provides the same functionality as a pre-place-and-route netlist. Formal verification tools do not require you to create any test vectors and can significantly accelerate verification efforts for large designs. Quartus II software versions 2.1 and later support the Cadence Conformal LEC formal verification tool flow. Support for the Synopsys Formality software is available in Quartus II software versions 4.2 and later.
 Design verification can be the longest process in developing multi-million-gate designs. Quartus II software reduces verification time by providing tight integration to register transfer level (RTL)-based simulation software from the leading third-party providers. Altera software subscriptions now include the Mentor Graphics® ModelSim®-Altera HDL simulator. For large designs requiring multiple design iterations, ModelSim-Altera software supports behavioral RTL simulation for pre-place-and-route functional verification of HDL code. ModelSim-Altera software also gives Quartus II software users full support for VHDL and Verilog HDL testbenches so you can perform automated and fully repeatable testing of large and complicated designs. More information is available in the Simulation section of the Quartus II Handbook .
SOPC designers must meet both chip-level and board-level timing requirements to obtain maximum system performance. Quartus II design software includes world-class, chip-level timing analysis capabilities and outputs SDO files for further analysis by third-party, board-level timing analysis tools to analyze system-level performance.
Altera has developed two methods to help you analyze your devices' internal nodes and I/O pins while operating in-system and at system speeds: SignalProbe debugging technology and SignalTap® II logic analysis. The SignalProbe and SignalTap II technologies fit seamlessly into any third-party synthesis flow and do not require any modifications to the HDL design source files.
To help accelerate the in-system debug process, Quartus II software now includes the chip planner and an in-system memory content editor feature that allows design changes to be implemented in-system in just minutes without performing a full design recompile.
SignalProbe Routing Technology
SignalProbe routing technology lets you route an internal node to an unused or reserved pin for analysis with an external scope or logic analyzer. SignalProbe technology leverages Altera’s FPGA advanced hardware architecture to enhance node visibility at a fraction of the time that a full design recompilation would require. Furthermore, the design’s original routing and timing are fully preserved. You can also pipeline individual SignalProbe signals using one or more registers to synchronize timing with other SignalProbe signals. Pipelining provides an accurate picture of the captured signals timing relationships. For more information refer to the Quick Design Debugging Using SignalProbe chapter of the Quartus II Handbook .
SignalTap II Logic Analysis for Hardware Verification
 For many designs on devices with high I/O ball-grid array (BGA) packages, system-level verification is very time consuming and sometimes extremely difficult. SignalTap II logic analysis facilitates the verification process by integrating the functionality of a logic analyzer within the software. The SignalTap II embedded logic analyzer supports the most channels, fastest clock speeds, and largest sample depths available. It now features the most advanced triggering capabilities available in an FPGA embedded logic analyzer, and the SignalTap II logic analyzer supports the highest number of channels and sample depths and the fastest acquisition clocks of any embedded logic analyzer in the programmable logic market. SignalTap II logic analysis allows your design team to capture a device’s internal node or I/O pin state in real time, operating at system speeds. With SignalTap II embedded logic analyzer, you can incrementally change or modify which nodes the analyzer is monitoring without performing a full design recompile. SignalTap II logic analysis enhances the verification process so designs can reach production faster.
Logic Analyzer Interface
The Logic Analyzer Interface (LAI) in Quartus II software connects and transmits internal signals buried within an FPGA to an external logic analyzer for analysis. The LAI debugs a large set of internal signals using a small number of output pins. In the LAI, the internal signals are grouped together, distributed to a user-configurable multiplexer, and then output to available I/O pins on their FPGA. Instead of having a one-to-one relationship between internal signals and output pins, the LAI maps many internal signals to one pin. The exact number of internal signals that you can map to an output pin varies based on the multiplexer settings in the LAI setting. For more information, refer to the In-System Debugging Using External Logic Analyzers chapter of the Quartus II Handbook .
The Quartus II software chip planner views the internal structure of Altera devices, incrementally edits logic element (LE) and I/O cell configuration, and generates new programming files in seconds—without recompiling a design. Using the Quartus II chip planner, in combination with the SignalTap II embedded logic analyzer and SignalProbe routing feature, can dramatically speed up your design verification process.
You can now easily perform “what if?” type experiments in-system in just seconds. Quartus II software enables FPGA memory contents and design constants to be updated in-system without recompiling a design or reconfiguring the rest of the FPGA.
The Quartus II PowerPlay power analysis feature estimates power consumption from early design concept through design implementation. You can use the PowerPlay early power estimator spreadsheet to estimate static and dynamic power consumption during the design concept stage, and then refine power estimations using the PowerPlay power analyzer feature during the design implementation stage. The PowerPlay power analyzer feature improves the accuracy of power consumption estimations by using device resource usage and place-and-route results, and by performing statistical analysis of expected design node activity rates. By adding optional functional simulation vectors or timing simulation vector input, you can expect even more accurate power consumption estimations. Additional information is available in the Power Estimation & Analysis section of the Quartus II Handbook.
The keys to developing systems with high-speed I/O signals are signal integrity and meeting stringent EMC requirements. Quartus II software can output design-specific I/O buffer information specification (IBIS) models that can be exported to third-party signal integrity and EMC analysis tools such as the Cadence SpectraQuest, and Mentor Graphics XTK, Hyperlynx, and Interconnectix software tools.
As a Quartus II software user, you can use a variety of third-party verification tools. Altera works closely with third-party companies that provide HDL simulation, design rule checker, static timing analysis, formal verification, and signal integrity analysis to ensure that you can take advantage of the latest verification tools and methodologies. A complete listing of third-party EDA vendors that support Altera devices is available on the Altera Commitment to Cooperative Engineering Solutions (ACCESSSM) website.
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