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Home > Products > Design Software > Quartus II > Verification Features Print This Page Subscribe to Email Quartus II Verification and Simulation Quartus® II software provides the most advanced CPLD, FPGA, and structured ASIC verification support available. In addition to integrating with all of the leading third-party verification tools and methodologies, Quartus II software provides: TimeQuest Timing Analyzer, this easy-to-use, ASIC-strength timing analysis tool with native SDC support is recommended for all new 90-nm designs and all 65-nm designs  Integrated power analysis with the PowerPlay power analysis and optimization technology Chip planner (floorplan and chip editor) and in-system memory content editor to implement design changes in-system in just minutes SignalTap® II embedded logic analyzer (supported by the incremental compilation feature to accelerate verification cycles) In-system sources and probes, enabling users to apply stimuli to their design and sample internal nodes during run time SignalProbe and logic analyzer interface In today’s team-based work environments, you must address a wide range of verification challenges related to combining hardware, embedded software, and high-speed I/O systems in system-on-a-programmable-chip (SOPC) design. SOPC design teams often include programmable logic device (PLD) hardware engineers, board-level hardware engineers, and teams of software engineers—each with their own verification needs. Quartus II software now gives you the most comprehensive verification solutions available for SOPC solutions and traditional PLD hardware design. Table 1 provides an overview of the available Quartus II software verification solutions. Quartus II Verification Methods has descriptions of the supported verification features. Table 1. Quartus II Software Verification Solutions Verification Method Description Quartus II Software Support or Subscription Support Third-Party Support Design Rule Checking Checks designs before synthesis and fitting for coding styles that could cause synthesis, simulation, or design migration problems. Quartus II software to HardCopy® device migration design rule checking Synopsys Leda Functional Verification Checks whether a design meets functional requirements before fitting. Quartus II software simulator ModelSim®-Altera® software Aldec Active HDL Rivera Cadence Incisive NC Desktop Family Mentor Graphics® ModelSim tool Synopsys VCS Testbench Generation Reduces amount of hand-generated test vectors. Waveform-to-testbench converter Testbench template generator   Static Timing Analysis Analyzes, debugs, and validates a design's performance after fitting. Quartus II software classic static timing analyzer Quartus II software TimeQuest timing analyzer Synopsys PrimeTime Timing Simulation Performs a detailed gate-level timing simulation after fitting. Quartus II software simulator ModelSim-Altera software Cadence NC-SIM Mentor Graphics ModelSim tool  Synopsys VCS Hardware or Software Co-Simulation Quickly simulates interaction between PLD hardware, embedded processor, memory, and peripherals. ModelSim-Altera software Mentor Graphics ModelSim tool  In-System Verification Reports behavior of internal nodes in-system and at system speeds. SignalTap II logic analyzer (supported by incremental compilation) SignalProbe feature Logic analyzer interface  Chip Planner (floorplan and chip editor) In-System Updating of Memory & Constants (PDF) Design Debugging Using In-System Sources and Probes(PDF) Synplicity Identify Board-Level Timing Analysis Verifies whether PLD and entire board meet system timing requirements.   Mentor Graphics Tau Signal Integrity Analysis and Electromagnetic Compatibility (EMC) Verifies that high-speed I/O signals will be transmitted reliably and within EMC guidelines. Quartus II software design-specific IBIS model generation Cadence SpectraQuest Mentor Graphics Interconnectix XTK Hyperlynx Synopsys HSPICE Formal Verification Identifies differences between source register transfer level (RTL) netlists and post place-and-route netlists without the user creating any test vectors.   Cadence Conformal LEC Synopsys Formality Power Estimation Estimates the power consumption of a device using your design operating characteristics. Quartus II PowerPlay power analysis and optimization technology can read in VCD file input from the third-party tools listed. Quartus II PowerPlay power analyzer ModelSim-Altera software Cadence NC-SIM Mentor Graphics ModelSim tool  Synopsys VCS Third-Party Verification Support With Quartus II software, you can use a variety of third-party verification tools. Altera works closely with third-party companies that provide HDL simulation, design rule checker, static timing analysis, formal verification, and signal integrity analysis to ensure that you can take advantage of the latest verification tools and methodologies. A complete listing of third-party EDA vendors that support Altera® devices is available on the EDA Partners web page. Related Links SignalTap II Embedded Logic Analyzer Verification (PDF) volume of the Quartus II Development Software Handbook. Rate This Page

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